The primitive IOBUFDS_DIFF_OUT_DCIEN_XP5 is only supported in XP5IO banks. It's function is the same as the IOBUFEDS_DIFF_OUT_DCIEN
primitive supported in HP IO banks, except when the IBUFDISABLE pin is asserted, its output behaves differently than the IOBUFDS_DIFF_OUT_DCIEN
in HP banks. Please pay special attention in the design that uses both IOBUFDS_DIFF_OUT_DCIEN and IOBUFDS_DIFF_OUT_DCIEN_XP5.
Port Descriptions
Port
Direction
Width
Function
DCITERMDISABLE
Input
1
Control to enable/disable DCI termination. This is generally used to reduce power in long periods of an idle state.
I
Input
1
Input of OBUF. Connect to the logic driving the output port.
IBUFDISABLE
Input
1
The IBUFDISABLE feature is not supported with this primitive in the UltraScale architecture.
This port must be tied to logic '0'.
IO
Inout
1
Bidirectional diff_p port to be connected directly to top-level inout port.
IOB
Inout
1
Bidirectional diff_n port to be connected directly to top-level inout port.
O
Output
1
Output path of the buffer.
OB
Output
1
Output path of the buffer.
TM
Input
1
3-state enable input for the p-side or master side signifying whether the buffer acts as an input or output.
This pin must be connected to the same signal as the TS input.
TS
Input
1
3-state enable input for the n-side or slave side signifying whether the buffer acts as an input or output.
This pin must be connected to the same signal as the TM input.
Design Entry Method
Instantiation
Yes
Inference
No
IP and IP Integrator Catalog
No
Available Attributes
Attribute
Type
Allowed Values
Default
Description
SIM_DEVICE
STRING
"ULTRASCALE", "ULTRASCALE_PLUS"
"ULTRASCALE_PLUS"
Set the device version for simulation functionality.
USE_IBUFDISABLE
STRING
"TRUE", "FALSE", "T_CONTROL"
"TRUE"
This attribute must be unspecified or set to "TRUE" if specified.
Related Information
Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
Vivado
Design Suite Properties Reference Guide (UG912)