Primitive: Differential Input/Output Buffer
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: BIDIR_BUFFER
Introduction
The IOBUFDS is a differential input/output buffer primitive. A logic-High on the T pin disables the output buffer. When the output buffer is 3-stated (T = High), the input buffer and any on-die receiver termination (uncalibrated or DCI) are ON. When the output buffer is not 3-stated (T = Low), any on-die receiver termination (uncalibrated or DCI) is disabled.
I/O attributes that do not impact the logic function of the component, such as IOSTANDARD, DRIVE, and SLEW, should be supplied to the top-level port via an appropriate property.
Logic Table
| Inputs | Bidirectional | Outputs | ||
|---|---|---|---|---|
| I | T | IO | IOB | O |
| X | 1 | Z | Z | No Change |
| 0 | 0 | 0 | 1 | 0 |
| I | 0 | 1 | 0 | 1 |
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I | Input | 1 | Input of OBUF. Connect to the logic driving the output port. |
| IO | Inout | 1 | Bidirectional diff_p port to be connected directly to top-level inout port. |
| IOB | Inout | 1 | Bidirectional diff_n port to be connected directly to top-level inout port. |
| O | Output | 1 | Output path of the buffer. |
| T | Input | 1 | 3-state enable input signifying whether the buffer acts as an input or output. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP and IP Integrator Catalog | No |
Available Attributes
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IOBUFDS: Differential Input/Output Buffer
-- Spartan UltraScale+
-- Xilinx HDL Language Template, version 2025.2
IOBUFDS_inst : IOBUFDS
port map (
O => O, -- 1-bit output: Buffer output
I => I, -- 1-bit input: Buffer input
IO => IO, -- 1-bit inout: Diff_p inout (connect directly to top-level port)
IOB => IOB, -- 1-bit inout: Diff_n inout (connect directly to top-level port)
T => T -- 1-bit input: 3-state enable input
);
-- End of IOBUFDS_inst instantiation
Verilog Instantiation Template
// IOBUFDS: Differential Input/Output Buffer
// Spartan UltraScale+
// Xilinx HDL Language Template, version 2025.2
IOBUFDS IOBUFDS_inst (
.O(O), // 1-bit output: Buffer output
.I(I), // 1-bit input: Buffer input
.IO(IO), // 1-bit inout: Diff_p inout (connect directly to top-level port)
.IOB(IOB), // 1-bit inout: Diff_n inout (connect directly to top-level port)
.T(T) // 1-bit input: 3-state enable input
);
// End of IOBUFDS_inst instantiation