The primitive IBUFE3_XP5 is only supported in XP5IO banks. It's function is the same as the IBUFE3
primitive supported in HP IO banks, except when the IBUFDISABLE pin is asserted, its output behaves differently than the IBUFE3
in HP banks. Please pay special attention in the design that uses both IBUFE3 and IBUFE3_XP5.
Port Descriptions
Port
Direction
Width
Function
I
Input
1
Diff_p Buffer Input. Connect to top-level p-side input port.
IBUFDISABLE
Input
1
Disables input path through the buffer and forces to a logic High. This feature is generally used to reduce power at times
when the I/O is idle for a period of time.
O
Output
1
Buffer output
OSC<3:0>
Input
4
Offset cancellation value
OSC_EN
Input
1
Offset cancellation enable
VREF
Input
1
Vref input from HPIO_VREF
Design Entry Method
Instantiation
Yes
Inference
No
IP and IP Integrator Catalog
No
Available Attributes
Attribute
Type
Allowed Values
Default
Description
SIM_DEVICE
STRING
"ULTRASCALE", "ULTRASCALE_PLUS"
"ULTRASCALE_PLUS"
Set the device version for simulation functionality.
SIM_INPUT_BUFFER_OFFSET
DECIMAL
-50 to 50
0
Offset value for simulation purposes.
USE_IBUFDISABLE
STRING
"FALSE", "T_CONTROL", "TRUE"
"FALSE"
Set this attribute to "TRUE" to enable the IBUFDISABLE pin.
Related Information
Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)
Vivado
Design Suite Properties Reference Guide (UG912)