Primitive: Differential Input Buffer With Complementary Outputs and Input Buffer Disable
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: INPUT_BUFFER
Introduction
The primitive IBUFDS_DIFF_OUT_IBUFDISABLE_XP5 is only supported in XP5IO banks. It's function is the same as the IBUFDS_DIFF_OUT_IBUFDISABLE primitive supported in HP IO banks, except when the IBUFDISABLE pin is asserted, its output behaves differently than the IBUFDS_DIFF_OUT_IBUFDISABLE in HP banks. Please pay special attention in the design that uses both IBUFDS_DIFF_OUT_IBUFDISABLE and IBUFDS_DIFF_OUT_IBUFDISABLE_XP5.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| I | Input | 1 | Diff_p Buffer Input. Connect to top-level p-side input port. |
| IB | Input | 1 | Diff_n Buffer Input. Connect to top-level n-side input port. |
| IBUFDISABLE | Input | 1 | The IBUFDISABLE feature is not supported with this primitive in the UltraScale architecture. This port must be tied to logic '0'. |
| O | Output | 1 | Buffer diff_p output |
| OB | Output | 1 | Buffer diff_n output |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP and IP Integrator Catalog | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| SIM_DEVICE | STRING | "ULTRASCALE", "ULTRASCALE_PLUS" | "ULTRASCALE_PLUS" | Set the device version for simulation functionality. |
| USE_IBUFDISABLE | STRING | "TRUE", "FALSE", "T_CONTROL" | "TRUE" | This attribute must be unspecified or set to "TRUE" if specified. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IBUFDS_DIFF_OUT_IBUFDISABLE_XP5: Differential Input Buffer With Complementary Outputs and Input Buffer Disable
-- Spartan UltraScale+
-- Xilinx HDL Language Template, version 2025.2
IBUFDS_DIFF_OUT_IBUFDISABLE_XP5_inst : IBUFDS_DIFF_OUT_IBUFDISABLE_XP5
generic map (
SIM_DEVICE => "ULTRASCALE", -- Set the device version for simulation functionality (ULTRASCALE)
USE_IBUFDISABLE => "TRUE" -- Must be set to "TRUE"
)
port map (
);
-- End of IBUFDS_DIFF_OUT_IBUFDISABLE_XP5_inst instantiation
Verilog Instantiation Template
// IBUFDS_DIFF_OUT_IBUFDISABLE_XP5: Differential Input Buffer With Complementary Outputs and Input Buffer Disable
// Spartan UltraScale+
// Xilinx HDL Language Template, version 2025.2
IBUFDS_DIFF_OUT_IBUFDISABLE_XP5 #(
.SIM_DEVICE("ULTRASCALE"), // Set the device version for simulation functionality (ULTRASCALE)
.USE_IBUFDISABLE("TRUE") // Must be set to "TRUE"
)
IBUFDS_DIFF_OUT_IBUFDISABLE_XP5_inst (
);
// End of IBUFDS_DIFF_OUT_IBUFDISABLE_XP5_inst instantiation