Primitive: Digitally Controlled Impedance Reset Component
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: DCI_RESET
Introduction
This design element is used to reset the digitally controlled impedance (DCI) state machine after configuration has been completed. By toggling the RST input to the DCIRESET primitive while the device is operating, the DCI state-machine is reset and both phases of impedance adjustment proceed in succession. All I/Os using DCI will be unavailable until the LOCKED output from the DCIRESET block is asserted.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| LOCKED | Output | 1 | DCI state-machine LOCK status output. When Low, DCI I/O impedance is being calibrated and DCI I/Os are unavailable. Upon a Low-to-High assertion, DCI I/Os are available for use. |
| RST | Input | 1 | Active-High asynchronous reset input to DCI state-machine. After RST is asserted, I/Os utilizing DCI will be unavailable until LOCKED is asserted. |
Design Entry Method
| Instantiation | Recommended |
| Inference | No |
| IP and IP Integrator Catalog | No |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- DCIRESET: Digitally Controlled Impedance Reset Component
-- Spartan UltraScale+
-- Xilinx HDL Language Template, version 2025.2
DCIRESET_inst : DCIRESET
port map (
LOCKED => LOCKED, -- 1-bit output: LOCK status output
RST => RST -- 1-bit input: Active-High asynchronous reset input
);
-- End of DCIRESET_inst instantiation
Verilog Instantiation Template
// DCIRESET: Digitally Controlled Impedance Reset Component
// Spartan UltraScale+
// Xilinx HDL Language Template, version 2025.2
DCIRESET DCIRESET_inst (
.LOCKED(LOCKED), // 1-bit output: LOCK status output
.RST(RST) // 1-bit input: Active-High asynchronous reset input
);
// End of DCIRESET_inst instantiation
Related Information
- Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861)