AXI32 - AXI32 - 2025.2 English - Primitive: AXI32 - UG1704

Spartan UltraScale+ Libraries Guide (UG1704)
Document ID
UG1704
Release Date
2025-12-17
Version
2025.2 English

Primitive: AXI32

Page-1 Process.507 AXI32 AXI32 Sheet.7 ARREADY AWREADY WREADY RVALID RLAST RID[7:0] RRESP[1:0] RDATA... ARREADYAWREADYWREADYRVALIDRLASTRID[7:0]RRESP[1:0]RDATA[31:0]BVALIDBID[7:0]BRESP[1:0] Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.48 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.70 Sheet.72 Sheet.3 CLK ARVALID ARID[7:0] ARADDR[27:0] ARLEN[3:0] ARSIZE[2:0] ARB... CLKARVALIDARID[7:0]ARADDR[27:0]ARLEN[3:0]ARSIZE[2:0]ARBURST[1:0]ARLOCKARCACHE[3:0]ARPROT[2:0]ARQOS[3:0]AWVALIDAWID[7:0]AWADDR[27:0]AWLEN[3:0]AWSIZE[2:0]AWBURST[1:0]AWLOCKAWCACHE[3:0]AWPROT[2:0]AWQOS[3:0]WVALIDWLASTWID[7:0]WDATA[31:0]WSTRB[3:0]RREADYBREADY Sheet.26 Sheet.73 X50161-040825 X50161-040825

Introduction

The AXI32 primitive is the hardened 32-bit AXI4 interface from the programmable logic (PL) to the platform management controller (PMC). The primitive supports run-time access to crypto blocks AES-GCM, SHA3, PUF, point multiplier for elliptic curve cryptography (ECC), true random number generator (TRNG), post-configuration flash programming, and eFUSE programming. The AXI32 primitive can be accessed in IP integrator (IPI) with the PMC Bridge IP or using the XPM_PMC_BRIDGE module to instantiate AXI32 in the user design.