The HLS compilation mode provides access to numerous features for the
development, optimization, analysis, and export of Vitis kernels (.xo) or Vivado IP
(.xci) files. Access the HLS mode command with the following command:
v++ -c --mode hls -h [options] <input_files...>Specify the HLS compilation options in a configuration file for the v++ command using the --config option. Place the HLS options under a section head of [HLS] in the config file. For example, the following
config file specifies the part, the source file, the test bench files, and the flow
target. part is not specified under the [HLS] header because this is a general option for the
v++ compiler.
part=xcvu11p-flga2577-1-e
[hls]
clock=8
flow_target=vitis
syn.file=../../src/dct.cpp
syn.top=dct
tb.file=../../src/out.golden.dat
tb.file=../../src/in.dat
tb.file=../../src/dct_test.cpp
tb.file=../../src/dct_coeff_table.txt
syn.output.format=xo
clock_uncertainty=15%
The following sections describe the HLS mode command options.