Description
Specifies a region of code, a protocol region, in which Vitis HLS does not insert clock operations unless the code explicitly specifies. The tool does not insert any clocks between operations in the region, including clocks that read or write to function arguments. The synthesized RTL strictly follows the order of read and writes.
A region of code can be created in the C/C++ code by enclosing the region in
braces "{ }" and naming it. The following defines a region named
io_section:io_section:{
...
lines of code
...
}You can specify a clock operation in C code using an ap_wait() statement. You can specify a clock operation in C++ code
using the wait() statement.
Tip: The
ap_wait and
wait statements have no effect on the
simulation of the design.Syntax
syn.directive.protocol=[OPTIONS] <location>The <location> specifies the location
(in the format function[/label]) where you define
the protocol region.
Options
-
mode=[floating | fixed] -
-
floating: Lets code statements outside the protocol region overlap and execute in parallel with statements in the protocol region in the final RTL. The protocol region remains cycle accurate, but outside operations can occur at the same time. This is the default mode. -
fixed: The fixed mode ensures that statements outside the protocol region do not execute in parallel with the protocol region.
-
Examples
The example code defines a protocol region,
io_section in function foo. The
following directive defines that region as a fixed mode protocol
region:syn.directive.protocol=mode=fixed foo/io_section