syn.directive.loop_merge - 2025.2 English - UG1702

Vitis Reference Guide (UG1702)

Document ID
UG1702
Release Date
2025-11-20
Version
2025.2 English

Description

Merges all loops into a single loop. Merging loops:

  • Reduces the number of clock cycles required in the RTL to transition between the loop-body implementations.
  • Allows implementation of loops in parallel (if possible).

The rules for loop merging are:

  • If the loop bounds are variables, they must have the same value (number of iterations).
  • If loops bounds are constants, the tool uses the maximum constant value as the bound of the loop being merged.
  • Loops with both variable bounds and constant bounds cannot be merged.
  • The code between merging loops cannot have side effects. Multiple executions of this code need to generate the same results.
    • a=b is allowed
    • a=a+1 is not allowed.
  • Loops cannot be merged when they contain FIFO reads. Merging changes the order of the reads. Reads from a FIFO or FIFO interface must always be in sequence.

Syntax

syn.directive.loop_merge=[options] <location>
  • <location> is the location (in the format function[/label]) at which the loops reside.

Options

force
Forces loops to be merged even when Vitis HLS issues a warning. Ensures that the merged loop functions correctly.

Examples

Merges all consecutive loops in function foo into a single loop.

syn.directive.loop_merge=foo

All loops inside loop_2 of function foo (but not loop_2 itself) are merged by using the force option.

syn.directive.loop_merge=force foo/loop_2