--advanced Options - --advanced Options - 2026.1 English - UG1702

Vitis Reference Guide (UG1702)
Document ID
UG1702
Release Date
2026-06-23
Version
2026.1 English

The --advanced.param and --advanced.prop options specify parameters and properties for use by the v++ command. When compiling or linking, these options offer fine-grain control over the hardware generated by the Vitis core development kit, and the hardware emulation process.

Specify arguments for the --advanced.xxx options as <param_name>=<param_value>. For example:

v++ --link -–advanced.param compiler.enableXSAIntegrityCheck=true 
-–advanced.prop kernel.foo.kernel_flags="-std=c++0x"
Tip: Vitis Compiler Configuration File contains the order of precedence between the command line and the config file. There are multiple entries in the config file. However, the --advanced commands described here have the opposite precedence. Config file commands take precedence over command-line arguments, and the last command encountered takes precedence over any earlier occurrences.

--advanced.param

--advanced.param <param_name>=<param_value>

Specifies advanced parameters as described in the following table.

Param Options

Table 1. Param Options
Parameter Name Valid Values Description
compiler.acceleratorBinaryContent Type: String

Default Value: <empty>

Design content to insert in the generated xclbin file. Valid options include bitstream, pdi, or dcp.

bitstream and pdi are mutually exclusive. pdi applies to Versal platforms, bitstreamapplies to non-Versal platforms.

Tip:

You can specify two values to have v++ generate two xclbin files: one containing a DCP file, and the other containing either a bitstream or PDI file. For example:

--advanced.param compiler.acceleratorBinaryContent=dcp,bitstream
--advanced.param compiler.acceleratorBinaryContent=dcp,pdi

This parameter is used while building the hardware target, this option applies to:

  • v++ --link
  • vpl.impl
  • xclbinutil
compiler.axiDeadLockFree Type: Boolean

Default Value: TRUE

 Avoid dead locks. This option is enabled by default for Vitis HLS.
compiler.​deadlockDetection Type: Boolean

Default Value: FALSE

 Enables detection of kernel deadlocks during the simulation run as part of hardware emulation. The tool posts an Error message to the console and the log file when the application is deadlocked:
// ERROR!!! DEADLOCK DETECTED at 42979000 ns! SIMULATION WILL BE STOPPED! //

The message is repeated until the deadlock is terminated. You must manually terminate the application to end the deadlock condition.

Tip: When deadlocks are encountered during simulation, you can open the kernel code in Vitis HLS for additional deadlock detection and debug capability.

Applies to:

  • v++ --compile
  • Vitis HLS
  • config_export
compiler.emulationMode=<mode> Type: String

func | rtl

 Indicates that the kernel need to be compiled as RTL code for use in hardware emulation and hardware design, or as a C functional model with a SystemC wrapper for use in hardware emulation.

This option applies to v++ --compile. The default is to compile the kernel as RTL code.
compiler.enableIncrHwEmu Type: Boolean

Default Value: FALSE

 Use to enable incremental compilation of the hardware emulation xclbin when there are minor changes made to the platform. This option enables a quick device binary rebuild for hardware emulation when the platform updates.

Applies to:

  • v++ --link
  • vpl.impl
compiler.​errorOnHoldViolation Type: Boolean

Default Value: TRUE

 After the last step of Vivado implementation, during timing analysis check, and clock scaling if needed. If hold violations are found, v++ quits and returns an error by default, and does not generate an xclbin. This parameter lets you over ride the default behavior.

Applies to:

  • v++ --link
  • vpl.impl
compiler.​interfaceRdBurstLen Type: Int Range

Default Value: 0

Specifies the expected length of AXI read bursts on the kernel AXI interface. This is used with option compiler.interfaceRdOutstanding to determine the hardware buffer sizes. Values are 1 through 256.

Applies to:

  • v++ --compile
  • Vitis HLS
  • config_interface
compiler.​interfaceWrBurstLen Type: Int Range

Default Value: 0

Specifies the expected length of AXI write bursts on the kernel AXI interface. This is used with option compiler.interfaceWrOutstanding to determine the hardware buffer sizes. Values are 1 through 256.

Applies to:

  • v++ --compile
  • Vitis HLS
  • config_interface
compiler.​interfaceRdOutstanding Type: Int Range

Default Value: 0

Specifies how many outstanding reads to buffer are on the kernel AXI interface. Values are 1 through 256.

Applies to:

  • v++ --compile
  • Vitis HLS
  • config_interface
compiler.​interfaceWrOutstanding Type: Int Range

Default Value: 0

Specifies how many outstanding writes to buffer are on the kernel AXI interface. Values are 1 through 256.

Applies to:

  • v++ --compile
  • Vitis HLS
  • config_interface
compiler.skipTimingCheckAndFrequencyScaling Type: Boolean

Default Value: FALSE

 This parameter causes the Vivado tool to skip the timing check and optional clock frequency scaling that occurs after the last step of implementation process, which is either route_design or post-route phys_opt_design.

Applies to:

  • v++ --link
  • vpl.impl
​compiler.userPreCreateProjectTcl Type: String

Default Value: <empty>

Specifies a Tcl script to run before creating the Vivado project in the Vitis build process.

Applies to:

  • v++ --link
  • vpl.create_project
​compiler.userPreSysLinkOverlayTcl Type: String

Default Value: <empty>

Specifies a Tcl script to run after opening the Vivado IP integrator block design, before running the compiler-generated dr.bd.tcl script in the Vitis build process.

Applies to:

  • v++ --link
  • vpl.create_bd
​compiler.userPostSysLinkOverlayTcl Type: String

Default Value: <empty>

Specifies a Tcl script to run after running the compiler-generated dr.bd.tcl script.

Applies to:

  • v++ --link
  • vpl.update_bd
​compiler.userPostDebugProfileOverlayTcl Type: String

Default Value: <empty>

Specifies a Tcl script to run after debug profile overlay insertion in Vivado IP integrator block design in the vpl.update_bd step.

Applies to:

  • v++ --link
  • vpl.updated_bd
compiler.​worstNegativeSlack Type: Float

Default Value: 0

 During timing analysis check, this specifies the worst acceptable negative slack for the design, specified in nanoseconds (ns). When negative slack exceeds the specified value, the tool might try to scale the clock frequency to achieve timing results. This specifies an acceptable negative slack value instead of zero slack.

Applies to:

  • v++ --link
  • vpl.impl
compiler.​xclDataflowFifoDepth Type: Int

Default Value: -1

Specifies the depth of FIFOs used in kernel data flow region.

Applies to:

  • v++ --compile
  • Vitis HLS
  • config_dateflow
hw_emu.aie_shim_sol_path Type: String

Default Value: <empty>

For use by Versal platforms, this option specifies the path to the AI Engine Interface Tile constraints file which is generated by the aiecompiler.

Used during simulation, compilation, and elaboration, the file provides a logical mapping to the physical interface. This is needed for third-party simulators like Mentor Graphics Questa Advanced Simulator or Cadence Xcelium Logic Simulation.
hw_emu.​compiledLibs Type: String

Default Value: <empty>

Uses mentioned clibs for the specified simulator.

Applies to Hardware Emulation and Debug.
hw_emu.​debugMode wdb

Default Value: wdb

The default value is WDB and runs simulation in waveform mode.

This option only works in combination with the -g or --debug options.

Applies to Hardware Emulation and Debug.
hw_emu.​enableProtocolChecker Type: Boolean

Default Value: FALSE

This option enables the lightweight AXI protocol checker (LAPC) during hardware emulation to verify the correctness of AXI interfaces.

Applies to Hardware Emulation and Debug.
hw_emu.json_device_file_path Type: String

Default Value: <empty>

For use by Versal platforms, this option specifies the path to the AI Engine JSON Device file located in the Vitis software installation area.

Used during simulation, compilation, and elaboration, the file specifies the size of the AI Engine array. This is needed for third-party simulators like Mentor Graphics Questa Advanced Simulator or Cadence Xcelium Logic Simulation.
hw_emu.platformPath Type: String

Default Value: <empty>

Specifies the path to the custom platform directory. The <platformPath> directory need to meet the following requirements to be used in platform creation:
  • The directory need to contain a subdirectory called ip_repo.
  • The directory need to contain a subdirectory called scripts and this scripts directory need to contain a hw_em_util.tcl file. The hw_em_util.tcl file need to have the following two procedures defined in it:
    • hw_em_util::add_base_platform
    • hw_em_util::generate_simulation_scripts_and_compile

Applies to Hardware Emulation and Debug.
hw_emu.post_sim_settings Type: String

This option specifies the path to a Tcl script that configures the Vivado simulator.

The tool runs the script after default configuration and before launching hardware emulation. You can use the Tcl script to override specific settings, or to custom configure the simulator as needed.

Applies to Hardware Emulation and Debug.
hw_emu.reduceHwEmuCompileTime Type: Boolean

Default Value: FALSE

 Move the generation of the top-level block design into the Generate Targets step of v++ --link.

Applies to Hardware Emulation and Debug.
hw_emu.​scDebugLevel none | waveform | log | waveform_and_log

Default Value: waveform_and_log

 Sets the TLM transaction debug level of the Vivado logic simulator (xsim).
  • NONE to disable TLM debug
  • LOG to dump TLM transaction log info into report file
  • WAVEFORM for enabling the TLM transaction waveform view
  • WAVEFORM_AND_LOG for both the Log Messages and Waveform view

Applies to Hardware Emulation and Debug.
hw_emu.simulator XSIM | QUESTA

Default Value: XSIM

 Uses the specified simulator for the hardware emulation run.

Applies to Hardware Emulation and Debug.
package.apuLinuxEdfMetadata

Path to a data file containing files used for device tree and BOOT.bin generation.

Default: use data contained in the fixed.xsa specified using the v++ -p --platform option.

 For designs that use base platforms prepared for Embedded Development Framework (EDF), you may optionally set --advanced.param package.apuLinuxEdfMetadata to specify or override a data file normally read from the fixed.xsa specified as the v++ -p --platform value. The data file is normally included in the extensible platform xsa used as the v++ link platform option and propagated to the fixed.xsa.
package.userDtsPath

Path to a user DTSI used for device tree and passed to sdtgen after the board dtsi file

Default: use only the board DTSI file.

For designs that use base platforms prepared for the Embedded Development Framework (EDF), you can optionally set --advanced.param package.userDtsPath=/path/to/user.dtsi to pass additional device tree information to sdtgen after the board .dtsi data.

By default, v++ -p reads a data file from the fixed.xsa specified by the v++ -p --platform value. This data file includes the information used for device tree generation, including board .dtsi data. v++ -p then invokes sdtgen and lopper, followed by dtc, to create the .dtb and .dtbo device tree files.
For example: 
--advanced.param compiler.addOutputTypes="hw_export"
Tip: This option can be specified in a configuration file under the [advanced] section head using the following format:
[advanced]
param=compiler.addOutputTypes="hw_export"

--advanced.prop

--advanced.prop <arg>

Specifies advanced kernel or solution properties for kernel compilation where <arg> is one of the values described the following table.

Table 2. Prop Options
Property Name Valid Values Description
kernel.<kernel_name>.​kernel_flags Type: String

Default Value: <empty>

Sets specific compile flags on the kernel <kernel_name>.
solution.​kernel_compiler_margin Type: Float

Default Value: 12.5% of the kernel clock period.

 The clock margin (in ns) for the kernel. This value is subtracted from the kernel clock period prior to synthesis to provide some margin for place and route delays.

--advanced.misc

--advanced.misc <arg>

Specifies advanced tool directives for kernel compilation.