The utility also reports the v++ command
line used to generate the xclbin. The Command Line section
gives the actual v++ command line used, while the Options
section displays each option used in the command line, but in a more readable format with
one option per line.
$ xclbinutil --input build_dir.hw_emu.xilinx_u250_gen3x16_xdma_4_1_202210_1/vadd.xclbin --info
XRT Build Version: 2.19.185 (2025.1)
Build Date: 2025-04-27 06:39:04
Hash ID: 6d79c5f0e8c3f0ca8c08d35f2cfe6908ca0752a3
------------------------------------------------------------------------------
Warning: The option '--output' has not been specified. All operations will
be done in memory with the exception of the '--dump-section' command.
------------------------------------------------------------------------------
Reading xclbin file into memory. File: build_dir.hw_emu.xilinx_u250_gen3x16_xdma_4_1_202210_1/vadd.xclbin
==============================================================================
XRT Build Version: 2.19.185 (2025.1)
Build Date: 2025-04-27 06:39:04
Hash ID: 6d79c5f0e8c3f0ca8c08d35f2cfe6908ca0752a3
==============================================================================
xclbin Information
------------------
Generated by: v++ (2025.1) on 2025-04-27-00:01:42
Version: 2.19.185
Kernels: vadd
Signature:
Content: HW Emulation Binary
UUID (xclbin): 65022735-bba0-8345-3e99-a17768a9913e
Sections: BITSTREAM, MEM_TOPOLOGY, IP_LAYOUT, CONNECTIVITY,
CLOCK_FREQ_TOPOLOGY, BUILD_METADATA,
EMBEDDED_METADATA, SYSTEM_METADATA,
GROUP_CONNECTIVITY, GROUP_TOPOLOGY
==============================================================================
Hardware Platform (Shell) Information
-------------------------------------
Vendor: xilinx
Board: u250
Name: gen3x16_xdma_4_1
Version: 202210.1
Generated Version: Vivado 2022.1 (SW Build: 3510589)
Created:
Thu Mar 31 07:42:58 2022 FPGA Device: xcu250
Board Vendor: xilinx.com
Board Name: xilinx.com:au250:1.4
Board Part: xilinx.com:au250:part0:1.4
Platform VBNV: xilinx_u250_gen3x16_xdma_4_1_202210_1
Static UUID: 00000000-0000-0000-0000-000000000000
Feature ROM TimeStamp: 0
Scalable Clocks
---------------
Name: DATA_CLK
Index: 0
Type: DATA
Frequency: 300 MHz
Name: KERNEL_CLK
Index: 1
Type: KERNEL
Frequency: 300 MHz
System Clocks
------
Name: ii_level1_wire_ulp_m_aclk_ctrl_00
Type: FIXED
Default Freq: 50 MHz
Name: ii_level1_wire_ulp_m_aclk_pcie_user_00
Type: FIXED
Default Freq: 250 MHz
Name: ii_level1_wire_ulp_m_aclk_freerun_ref_00
Type: FIXED
Default Freq: 100 MHz
Name: ss_ucs_aclk_kernel_00
Type: SCALABLE
Default Freq: 300 MHz
Requested Freq: 0 MHz
Achieved Freq: 0 MHz
Name: ss_ucs_aclk_kernel_01
Type: SCALABLE
Default Freq: 500 MHz
Requested Freq: 0 MHz
Achieved Freq: 0 MHz
Memory Configuration
--------------------
Name: bank0
Index: 0
Type: MEM_DDR4
Base Address: 0x4000000000
Address Size: 0x400000000
Bank Used: No
Name: bank1
Index: 1
Type: MEM_DDR4
Base Address: 0x5000000000
Address Size: 0x400000000
Bank Used: Yes
Name: bank2
Index: 2
Type: MEM_DRAM
Base Address: 0x6000000000
Address Size: 0x400000000
Bank Used: No
Name: bank3
Index: 3
Type: MEM_DRAM
Base Address: 0x7000000000
Address Size: 0x400000000
Bank Used: No
Name: PLRAM[0]
Index: 4
Type: MEM_DRAM
Base Address: 0x3000000000
Address Size: 0x20000
Bank Used: No
Name: PLRAM[1]
Index: 5
Type: MEM_DRAM
Base Address: 0x3000200000
Address Size: 0x20000
Bank Used: No
Name: PLRAM[2]
Index: 6
Type: MEM_DRAM
Base Address: 0x3000400000
Address Size: 0x20000
Bank Used: No
Name: PLRAM[3]
Index: 7
Type: MEM_DRAM
Base Address: 0x3000600000
Address Size: 0x20000
Bank Used: No
Name: HOST[0]
Index: 8
Type: MEM_DRAM
Base Address: 0x2000000000
Address Size: 0x400000000
Bank Used: No
==============================================================================
Kernel: vadd
Definition
----------
Signature: vadd (void* in1, void* in2, void* out, unsigned int size)
Ports
-----
Port: M_AXI_GMEM0
Mode: master
Range (bytes): 0xFFFFFFFF
Data Width: 32 bits
Port Type: addressable
Port: M_AXI_GMEM1
Mode: master
Range (bytes): 0xFFFFFFFF
Data Width: 32 bits
Port Type: addressable
Port: S_AXI_CONTROL
Mode: slave
Range (bytes): 0x3C
Data Width: 32 bits
Port Type: addressable
--------------------------
Instance: vadd_1
Base Address: 0x1d010000
Argument: in1
Register Offset: 0x10
Port: M_AXI_GMEM0
Memory: bank1 (MEM_DDR4)
Argument: in2
Register Offset: 0x1C
Port: M_AXI_GMEM1
Memory: bank1 (MEM_DDR4)
Argument: out
Register Offset: 0x28
Port: M_AXI_GMEM0
Memory: bank1 (MEM_DDR4)
Argument: size
Register Offset: 0x34
Port: S_AXI_CONTROL
Memory: <not applicable>
==============================================================================
Generated By
------------
Command: v++
Version: 2025.1 - 2025-04-27-00:01:42 (SW BUILD: 6117406)
Command Line: v++ --debug --input_files _x.hw_emu.xilinx_u250_gen3x16_xdma_4_1_202210_1/vadd.xo --link --optimize 0 --output ./build_dir.hw_emu.xilinx_u250_gen3x16_xdma_4_1_202210_1/vadd.link.xclbin --platform xilinx_u250_gen3x16_xdma_4_1_202210_1 --report_level 0 --save-temps --target hw_emu --temp_dir ./_x.hw_emu.xilinx_u250_gen3x16_xdma_4_1_202210_1
Options: --debug
--input_files _x.hw_emu.xilinx_u250_gen3x16_xdma_4_1_202210_1/vadd.xo
--link
--optimize 0
--output ./build_dir.hw_emu.xilinx_u250_gen3x16_xdma_4_1_202210_1/vadd.link.xclbin
--platform xilinx_u250_gen3x16_xdma_4_1_202210_1
--report_level 0
--save-temps
--target hw_emu
--temp_dir ./_x.hw_emu.xilinx_u250_gen3x16_xdma_4_1_202210_1
==============================================================================
User Added Key Value Pairs
--------------------------
<empty>
==============================================================================
Leaving xclbinutil.