The Schedule Viewer provides a detailed view of the synthesized RTL. It shows each function operation and control step, along with the clock cycle in which each one executes. Use this viewer to identify loop dependencies that limit parallelism, timing violations, and data dependencies.
- The left vertical axis shows the names of operations and loops that the RTL hierarchy implements as logic. The viewer lists operations in topological order, which indicates that an operation on one line can only be driven by an operation on a previous line. Depending on the violation type, the Schedule Viewer shows additional information for each operation.Tip: Right-click an operation and use Goto Source to open the source code.
- The top horizontal axis shows clock cycles in consecutive order.
- The vertical dashed line in each clock cycle shows the reserved portion of the clock period for clock uncertainty. This time is reserved for Vivado back-end processes such as place and route.
- Each operation appears as a gray box in the table. For function calls, the cycle information matches the operation latency. Multi-cycle operations appear as gray boxes with a horizontal line through the center.
- The Schedule Viewer also shows general operator data dependencies as solid blue lines. When you select an operation, solid blue arrows highlight the specific operator dependencies. This view supports detailed dependency analysis. A green dotted line indicates an inter-iteration data dependency. Memory dependencies appear as gold lines.Tip: By default, the viewer shows all dependencies (blue lines) between operations in the critical timing path.
- On the far right, the HLS Module Hierarchy lets you quickly navigate the design hierarchy.
In the following figure, the loop COL_DCT_LOOP_DCT_OUTER_LOOP shows its initiation interval (II) in the loop bar. The tool pipelines this loop and explicitly displays the II in the loop bar. The schedule viewer displays each pipelined loop in an expanded view and shows one full iteration. A thick clock boundary on the loop marker indicates the overlap defined by the II. In this example, the loop marker spans the total latency of one iteration, which is six clock cycles.
The Schedule Viewer includes a menu bar at the top of the report with the following features:
- Zoom In, Zoom Out, and Zoom Fit commands
- A search field to find specific operations or steps and move through matching objects
- Legend command for the display
You can quickly locate timing violations and II violations from the toolbar menu in the Module Hierarchy. To locate the operations that cause a violation in the source code, right-click the operation and click Goto Source. A timing violation occurs when a path of operations requires more time than the available clock cycle. In the Schedule Viewer, the problematic operation appears in a red box.
Properties View
At the bottom of the Schedule Viewer, the Properties pane shows details for the selected function, loop, or operation.
| Term | Description |
|---|---|
| Initiation Interval (II) | Number of clock cycles before the function or loop can accept new input data. |
| Loop Iteration Latency | Number of clock cycles required to complete one loop iteration. |
| Latency | Number of clock cycles, and the corresponding time, required for the function to compute all output values or for the loop to complete all iterations. |
| Name | Name of the function or loop. |
| Pipelined | Indicates whether the function or loop is pipelined in the RTL design. |
| Slack | Timing slack for the function or loop. |
| Tripcount | Number of loop iterations. |
| Resource Utilization | Number of BRAM, DSP, LUT, and FF resources used to implement the function or loop. |
| Term | Description |
|---|---|
| Bitwidth | Bit width of the operation. |
| Impl | Implementation used for the specified operation or storage. |
| Name | Name of the operation. |
| Op Latency | Default or specified latency for the bound operation or storage. |
| Opcode | Scheduled operation, such as add, sub, or mult. For more information, see the BIND_OP or BIND_STORAGE pragmas or directives. |
| Schedule Delay | Delay associated with the operation. |
Memory Schedule Viewer
The Memory Schedule viewer helps you understand how HLS schedules memory accesses. You can find it in the bottom section of the Schedule Viewer, next to the Properties tab. You can cross-probe variables between the Memory Schedule viewer and the Schedule Viewer in either direction. To cross-probe from the Schedule Viewer to the source code, right-click a variable and select Goto Source.