Make sure the HLS component is active in the Flow Navigator, or select it from the Component menu to make it the active component. The Flow Navigator can now run C Simulation, C Synthesis, C/RTL Co-simulation, Packaging, and Implementation to build and analyze the HLS component. Select Run beneath the Implementation heading in the Flow Navigator.
When the HLS compiler reports high‑level synthesis results, it estimates projected clock frequency and resource utilization. The tool does not know final optimizations or routing delays in the synthesized or implemented design. For a better analysis of the RTL design, run Vivado synthesis, place and route on the generated RTL design. Review the results of timing and resource utilization.
Configure Implementation
You can configure Vivado synthesis and implementation by using the Implementation section of the Config File Editor or by editing the HLS config file directly.
The configuration commands for Implementation include:
- vivado.flow
- Runs only synthesis or both synthesis and implementation. Synthesis alone
runs faster than both synthesis and implementation but is less detailed. The
default is
syn. - vivado.rtl
- Specifies the language when running Vivado out-of-context flow. The default is Verilog.
- vivado.clock
- Specifies the clock period during synthesis or implementation. Specifies the default clock when creating the HLS component if you do not provide this value.
- vivado.impl_strategy
- Specifies the strategy to employ in the implementation run. Use only in the implementation run for resource utilization and timing estimates. Does not affect the Vivado IP or Vitis kernels.
- vivado.max_timing_paths
- Species the number of timing paths to extract from the Timing Summary report. Returns the number of worst case paths.
- vivado.optimization_level
- Manages the optimizations the Vivado tool performs. Higher settings apply more optimizations and increase runtime.
- vivado.pblock
- Specifies a Pblock range or value to use during placement and routing to limit the area available for the design.
- vivado.phys_opt
- Specifies the physical optimization to run. Choices include:
none,place,route, andall. - vivado.report_level
- Defines the report-level generated during synthesis or implementation. The report can include the utilization and timing summary, timing path details, or a failfast report, which is the default.
- vivado.synth_design_args
- Specifies options for the
synth_designcommand. - vivado.synth_strategy
- Specifies the strategy to employ in the Vivado synthesis run.
Run Implementation
With the Implementation setup defined in the config file you are
ready to select Run from the
Flow Navigator. You
can track the progress of the implementation run in the Output window. The transcript for the run
will have the top function name as <component-name>::implementation as shown below.
vitis-run --mode hls --impl command. After the implementation completes, the tool displays the Implementation finished successfully message at the end of the transcript. Find the Reports folder under the IMPLEMENTATION heading. The following are details of the reports.
- Summary: reports the command line used and the time stamp on the results
- RTL Synthesis: reports the results of synthesis including resource use and timing
- Place and Route: see Implementation Report