RTL Configuration - RTL Configuration - 2026.1 English - UG1702

The syn.rtl commands configure various attributes of the compiled RTL, the type of reset used, and the encoding of the state machines. The commands also allow you to use specific identification in the RTL. By default, these options are apply to the top-level design and all RTL blocks within the design.

syn.rtl.cosim_trace_generation

Generates test vectors during hardware emulation in the Vitis tool flow. The option applies when the kernel synthesizes as a Vitis kernel. The process is useful C/RTL Co-simulation test bench in future design iterations.

syn.rtl.cosim_trace_generation=1

syn.rtl.deadlock_detection

Enables simulation or synthesis deadlock detection in the top-level RTL of an exported IP/XO file. The options are as follows:

• none: Disables deadlock detection.
• sim: Enables deadlock detection only for simulation/emulation. This is the default setting.
• hw: Enables detection in synthesized RTL IP. Adds ap_local_deadlock and ap_local_block signals to the IP to enable local and global deadlock detection.

syn.rtl.deadlock_detection=hw

syn.rtl.deadlock_diagnosis

Enables deadlock detection diagnosis for Vitis kernels (.xo) during hardware emulation of the Application.

syn.rtl.deadlock_diagnosis=1

syn.rtl.fsm_encoding

Specifies the 'fsm_encoding' RTL attribute value to guide RTL synthesis. The options are as follows:

• auto: Allow the RTL Synthesis tool to determine the best state machine encoding
• gray: Uses gray state machine encoding.
• johnson: Uses johnson state machine encoding.
• one_hot: Uses one_hot state machine encoding.
• sequential: Uses sequential state machine encoding.
• none: Disables state machine encoding. The state machine is synthesized exactly using the state code specified in the RTL (which is one_hot).

syn.rtl.fsm_encoding=gray

syn.rtl.fsm_safe_state

Specify the 'fsm_safe_state' RTL attribute value to guide RTL synthesis. This attribute can affect the quality of synthesis results, typically resulting in less performance with greater area. The options are as follows:

• auto_safe_state: Implies Hamming-3 encoding.
• default_state: Return the state machine to the default state.
• power_on_state: Return the state machine to the POWER_ON state.
• reset_state: Return the state machine to the RESET state.
• none: If you do not add the attribute to RTL, the state machine excludes safe state logic.

syn.rtl.fsm_safe_state=auto_safe_state

syn.rtl.header

This option specifies a file whose contents the tool inserts at the beginning of all generated RTL files. The option allows you to ensure that the generated RTL files contain user specified content.

syn.rtl.header=../../myHeader.txt

syn.rtl.kernel_profile

Add top level event and stall ports required by kernel profiling.

syn.rtl.kernel_profile=1

Important: This option relates to the v++ -c --profile.stall command. You must manually add this option to the HLS component to ensure the stall profiling is available for the linked application.

syn.rtl.module_auto_prefix

Specifies the top level function name as the prefix value for generated RTL modules. The tool ignores this option if you also specify syn.rtl.module_prefix. This tool enables this setting by default.

syn.rtl.module_auto_prefix=1

syn.rtl.module_prefix

Specifies a prefix to be used for all generated RTL module names. Use this to override the default module prefix of the top-level function.

syn.rtl.module_prefix=newTop

syn.rtl.mult_keep_attribute

Enables keep attribute.

syn.rtl.mult_keep_attribute=1

syn.rtl.register_all_io

Uses a register by default for all I/O signals.

syn.rtl.register_all_io=1

syn.rtl.register_reset_num

Number of registers to add to reset signal.

syn.rtl.register_reset_num=2

syn.rtl.reset

The RTL—and therefore the bitstream—always initializes variables to the same values as in the C/C++ code. The system performs this initialization only at power-on and does not repeat it when the design resets.

Apply this setting with the -reset option to determine how registers and memories are reset.

• none: Does not add resets to the design.
• control: Resets control registers, such as those used in state machines and those used to generate I/O protocol signals. This is the default setting.
• state: Resets control registers and registers or memories derived from static or global variables in the C/C++ code. Any static or global variable initialized in the C/C++ code resets to its initialized value.
• all: Resets all registers and memories in the design. Any static or global variable initialized in the C/C++ code is reset to its initialized value.

syn.rtl.reset=state

syn.rtl.reset_async

Causes all registers to use an asynchronous reset. If you do not specify this option, the tool uses a synchronous reset.

syn.rtl.reset_async=1

syn.rtl.reset_level

Defines the polarity of the reset signal to be either active-Low or active-High. The default setting is active-High.

syn.rtl.reset_level=low

Tip: The AXI protocol requires an active-Low reset. If your design uses AXI interfaces, the Vitis tool defines this reset level with a warning if the syn.rtl.reset_level is active-High.