Ports - Ports - 2026.1 English - UG1702

Vitis Reference Guide (UG1702)

Document ID
UG1702
Release Date
2026-06-23
Version
2026.1 English

Reports the memory and control ports used by the kernel.

=== Port ===
name: M_AXI_GMEM
mode: master
range: 0xFFFFFFFF
dataWidth: 32
portType: addressable
base: 0x0

=== Port ===
name: M_AXI_GMEM1
mode: master
range: 0xFFFFFFFF
dataWidth: 32
portType: addressable
base: 0x0

=== Port ===
name: S_AXI_CONTROL
mode: slave
range: 0x1000
dataWidth: 32
portType: addressable
base: 0x0