You can find the results of Synthesis, Place and Route results in the Implementation Report. The report include the following elements.
- General Information
- Provides general information related to the design and implementation.
- Run Constraints and Options
- Reports the RTL Synthesis and/or the Place & Route run's constraints.
- Resource Usage/Final Timing
- Reports a summary of the resources and timing achieved by either the RTL Synthesis or the Place & Route run. Provides a very high-level overview of the resource utilization and status on timing goals. The information in the succeeding sections provide details useful in debugging timing issues.
- Resources
- Displays a detailed per-module split up of resource. Can also show the original variable and source location information from the source code. If a particular resource is the result of a user-specified pragma, this resource is also in the table. You can relate your C code with the synthesized RTL implementation. Inspecting this report is very beneficial as this is after Vivado synthesized the design. Therefore, functional blocks like DSPs and other logic units are all instantiated in the circuit.
- Fail Fast
- Helps your investigation in specific issues the tool encountersencountered
by the tool. In the fail fast report, look into anything with the Status of
REVIEW to improve
the implementation and timing closure. Different sections of the fail fast
report include the following.
- Design Characteristics: The default utilization guidelines are based on SSI technology devices and can be relaxed for non-SSI technology devices. Designs with one or more REVIEW checks are feasible but are difficult to implement.
- Clocking Checks: These checks are critical and must be addressed.
- LUT and Net Budgeting: Use a conservative method to better predict which logic paths are unlikely to meet timing after placement with high device utilization.
Figure 1. Design Characteristics
- Timing Paths
- The Timing Paths reports show the timing critical paths that result in the worst slack for the design. By default, the tool will show the top 10 worst negative slack paths. Each path in the table has detailed information that shows the combination path between one flip-flop to another.
- You must break these long combinational paths to address the timing issues.
Analyze these paths and map these paths back to your C code. Using these paths
and the resources table can help in determining and correlating the path back to
your source code.
In the following figure, the top 10 negative slack paths in the Place & Route report have higher logic levels compared to after RTL Synthesis. The max fanout became worse. This clearly shows how congestion in the design is causing high logic levels and higher fanouts which in turn causes issues for meeting timing. Use these clues to modify your design to remove some of this congestion. You can rewrite the C code or change design decisions with respect to BRAM/LUTRAM/URAM resources.
Figure 2. Timing Paths Report