HLS Pragmas - HLS Pragmas - 2026.1 English - UG1702

Optimizations in Vitis HLS

In the AMD Vitis™ software platform, a kernel defined in the C/C++ language must be compiled into the register transfer level (RTL) that can be implemented into the programmable logic of an AMD device. The v++ compiler calls the Vitis High-Level Synthesis (HLS) tool to synthesize the RTL code from the kernel source code.

The HLS tool works with the Vitis IDE project without interaction. The HLS tool also provides pragmas you can use to:

• Optimize the design
• Reduce latency
• Improve throughput performance
• Reduce area and device resource usage of the resulting RTL code

Add these pragmas directly to the kernel source code.

The HLS pragmas include the optimization types specified in the following table.

For detailed pragma information, refer to the Vitis High-Level Synthesis User Guide (UG1399).