In an HLS Component, the tool synthesizes a C or C++ function into RTL code for implementation in the programmable logic (PL) region of an AMD Versal™ adaptive SoC, AMD Zynq™ MPSoC, or AMD FPGA device. You can build, simulate, analyze and debug an HLS Component as a standalone component in a bottom-up design flow. See the creation of an HLS Component in Managing the Vitis HLS Components in the Vitis Unified IDE.
You can add the HLS Component to a System project as part of an embedded system design. You can also add it for application acceleration in a data center. See Building and Running the System in the Data Center Acceleration using Vitis (UG1700) for the use of an HLS Component in a larger system design. Also see Vitis unified IDE as described under Creating a System Project for Heterogeneous Computing.