In an HLS component, the tool synthesizes a C or C++ function into RTL code for implementation in the programmable logic (PL) region of an AMD Versal™ adaptive SoC, AMD Zynq™ MPSoC, or AMD FPGA device. HLS components can be built, simulated, analyzed, and debugged as a standalone component in a bottom-up design flow. The creation of an HLS component is described in Managing the Vitis HLS Components in the Vitis Unified IDE.
The HLS component can be added to a System project as part of an embedded system design, or for application acceleration in a data center. The use of an HLS component in a larger system design is described in this document under Building and Running the System in the Data Center Acceleration using Vitis (UG1700) , or in the Vitis unified IDE as described under Creating a System Project for Heterogeneous Computing.