The AMD Vitis™ Unified IDE and
v++ common command line allows you to create
an HLS component using bottom-up design techniques. The procedure ensures the
component meets design requirements before integrating it with other elements into a
system design.
In an HLS component, the Vitis tool synthesizes a C or C++ function into RTL code for implementation in the
programmable logic (PL) region of the following devices.
- AMD Versal™ adaptive SoC
- AMD Zynq™ MPSoC, or
- AMD FPGA.
You can use an HLS component to develop and export the following components.
- Integration of Vivado IP into hardware designs using the Vivado Design Suite and the Embedded Software Development flow as described in Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400).
- HLS PL modules for use in hetergeneous compute systems and Data Center application acceleration as described in Embedded Design Development Using Vitis (UG1701).
The following steps illustrate the development of the C++ function.
- Architect the C/C++ algorithm based on Design Principles in the Vitis HLS User Guide (UG1399).
- Verify the logic of the source code with a C test bench (C-Simulation).
- Generate the RTL from the source code (C-Synthesis).
- Verify the generated RTL module with the C test bench and RTL logic simulation (C/RTL Co-Simulation).
- Review and analyze the HLS synthesis reports and co-simulation reports (Analyze).
- Repeat the previous steps until performance goals are met.
Figure 1.
Vitis HLS Development Flow
The HLS component implements the design based on the target flow, tool configuration, configuration commands, and optimization pragmas or directives you specified. The following sections describe creating and building the HLS component.