Vitis Reference Guide (UG1702) - 2024.2 English

Document ID: UG1702
Release Date: 2024-11-13
Version: 2024.2 English

Navigating Content by Design Process
Vitis Commands and Utilities
Launching the Vitis Unified IDE
Launch Options
v++ Command
v++ General Options
v++ Compilation Options
v++ General Compilation Options
v++ Mode AI Engine
AI Engine Options
CDO Options
Compiler Debugging Options
Design Rule Check Options
File Options
Module Specific Options
Event Tracing Options
Optimization Options
Miscellaneous Options
v++ Mode HLS
HLS General Options
Array Partition Configuration
Array Stencil Configuration
C-Simulation Configuration
Co-Simulation Configuration
Compile Options
Dataflow Configuration
Debug Options
Interface Configuration
Package Options
Operator Configuration
RTL Configuration
Schedule Setting
Storage Configuration
Implementation Configuration
Unroll Setting
HLS Optimization Directives
syn.directive.aggregate
syn.directive.alias
syn.directive.allocation
syn.directive.array_partition
syn.directive.array_reshape
syn.directive.bind_op
syn.directive.bind_storage
syn.directive.dataflow
syn.directive.dependence
syn.directive.disaggregate
syn.directive.expression_balance
syn.directive.function_instantiate
syn.directive.inline
syn.directive.interface
syn.directive.latency
syn.directive.loop_flatten
syn.directive.loop_merge
syn.directive.loop_tripcount
syn.directive.occurrence
syn.directive.performance
syn.directive.pipeline
syn.directive.protocol
syn.directive.reset
syn.directive.stable
syn.directive.stream
syn.directive.top
syn.directive.unroll
HLS Pragmas
v++ Linking and Packaging Options
--advanced Options
--clock Options
--connectivity Options
--debug Options
--drc Options
--linkhook Options
--package Options
--profile Options
--vivado Options
Vitis Compiler Configuration File
Using the Message Rule File
emconfigutil Utility
kernelinfo Utility
Kernel Definition
Arguments
Ports
launch_emulator Utility
Versal PS and PMC Arguments for QEMU
Zynq UltraScale+ MPSoC PS and PMU Arguments for QEMU
Zynq 7000 PS Arguments for QEMU
manage_ipcache Utility
package_xo Command
RTL Kernel XML File
platforminfo Utility
Basic Platform Information
Hardware Platform Information
Interface Information
Clock Information
Valid SLRs
Resource Availability
Memory Information
Feature ROM Information
Software Platform Information
Platform info for xilinx_zcu104_base_202010_1
vitis-run Command
xbutil Utility
xbmgmt Utility
xclbinutil Utility
xclbin Information
Hardware Platform Information
Clocks
Memory Configuration
Kernel Information
Tool Generation Information
xrt.ini File
Using the Vitis Unified IDE
Migration to Vitis Unified IDE
Migrating Vitis Classic IDE Graph Applications to Vitis Unified IDE
Launching Vitis Unified IDE
Vitis Unified IDE View and Feature
Vitis Component View
Deep Json Based Component Display
Search View
Source Control
Source Control
Add New File for Source Control
Add Components for Source Control
Commit the Changes
Push the Project to the Remote Repository
Relative Path Support
Debug View
Example View
Code View and Smart Editor
Issue and source code cross-probing
Problem View
Preferences
Settings
Keyboard Shortcuts, Command Palette, and Quick Find
Parallel Compiling
Notification for File Change
New Feature Preview
Workspace Journal
External Lopper Support
Creating an AI Engine Component
Creating an HLS Component
Creating an Application Component
Creating a Platform Component
Embedded Software Development Flow
Creating an Embedded Application Component
Command-line to Create an Embedded Application Component
Creating a System Project for Heterogeneous Computing
System Project Structure
Creating a System Project
Creating a System Project from Examples
Managing Components in System Projects
Defining the HW_Link System Configuration
Defining the Package Configuration
Building the System Project
Launching Run or Debug of the System Project
Debugging the System Project
Creating a Bare-metal System
Migrating Command-line Projects to the Vitis Unified IDE
Debugging the System Project and AI Engine Components
Launching Debug in the Vitis Unified IDE
Component Based Flow Design Debug
Hardware Debug from the Vitis IDE
Bare-Metal Debug from the Vitis Unified IDE
Using the Debug Environment
Watchpoints
Variable View and Memory Inspector
Register Inspector
Disassembly View
Multi-Kernel Debug
Viewing Data from Buffer Port Interfaces
Viewing Data from Stream Interfaces
AI Engine Pipeline View
Programming Device and Flash Memory
Vitis Interactive Python Shell
Auto-Completion of Python Statements
Basic Commands supported in Interactive mode
Commands to Edit a File
Commands to Run Python Scripts
Setting and Listing Environment Variables
Command to Display History
Command to Search the History
Command to Display Execution Time
Command to Clear the Session
Library Function References
Python API: Managing Vitis IDE Components
Create and Build AI Engine Component
Create and Build HLS Component
Create and Build System Project
Create and Build Platform Component
Create and Build Application Component
Vitis IDE Examples
Managing the Vitis HLS Components in the Vitis Unified IDE
Using the RTL Blackbox Wizard
C++ Model and Header Files
RTL IP Definition
Using Code Analyzer
Running C Synthesis
Output of C Synthesis
Synthesis Summary
Function Call Graph
Schedule Viewer
Dataflow Viewer
Running C/RTL Co-Simulation
Output of C/RTL Co-Simulation
Viewing Simulation Waveforms
Timeline Trace Viewer
Packaging the RTL Design
Running Implementation
Implementation Report
Cloning HLS Components
Component Comparison Feature
L1 Library Wizard Flow
Creating HLS Components from the Command Line
Opening HLS Component Flow Step Reports
Managing the AI Engine Component in the Vitis Unified IDE
Using the Vitis Unified IDE to Build and Simulate AI Engine Components
Creating an AI Engine Component
Defining the AI Engine Configuration File
Importing Files
Vitis Unified IDE Examples
Building the AI Engine Component
Viewing AI Engine Microcode
Managing AI Engine Components with the Python Command Line Interface
Using Python APIs to Manage AI Engine Components
Using APIs in a Python Script
Simulating and Debugging the AI Engine Component
Enabling Trace in AI Engine Based Simulation
Enabling AI Engine Profile
Extracting Throughput and Latency Estimates using Python CLI
Enabling AI Engine Pipeline
Debugging an AI Engine Component
Generating AI Engine Prototype Code
Single Kernel Development
Exporting Summary Tables from the Analysis View
Enabling Third-Party Simulators in the Vitis IDE
Working with the Analysis View (Vitis Analyzer)
Configuring the Analysis View
Open Summary Reports
Analysis View Window Manager
Viewing AI Engine Compilation Summary Reports
Viewing AI Engine Graphs and Arrays
Graph and Array Details
Kernels
I/O
Buffers
Ports
Nets
FIFO Depth Evaluation
Tiles
Interface Channels
Compilation Summary
AI Engine Kernel Stack and Heap Reports
Importing JSON Output Files
Additional Information
Output Structure of the Vitis Tools
Output Directories of the v++ Command
Output Directories of v++ -c --mode aie
Output Directories of v++ -c --mode hls
Output Directories of the Vitis Unified IDE
Python XSDB Commands
Breakpoints
Connections
Device
Download
IPI
JTAG
Memory
Miscellaneous
Registers
Reset
Running
STAPL
Streams
SVF
TFile
Usage Examples
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

Back to home page