Vitis Software Platform Installation - 2025.2 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)

Document ID: UG1701
Release Date: 2025-11-20
Version: 2025.2 English

Getting Started with Vitis Unified Software Platform
Navigating Content by Design Process
Vitis Software Platform Installation
Installing the Vitis Software Platform
Installing Xilinx Runtime and Platforms
Installing Embedded Platforms
Setting Up the Vitis Environment
Introduction to Vitis
Vitis Key Concepts
Vitis Tools Overview
Vitis Unified IDE
Compilers
Linker
Packager
Analyzer
Debugger
Tutorials and Examples
Vitis Flows and Build Environment
Workflow
Vitis Integrated Flow
Vitis Export to Vivado Flow
Vitis Subsystem Flow
Understanding the Vitis Build Flow
Vitis IDE Workspace
Command Line Recommendations
Files and Directories
Vivado and Vitis System Level Dependencies and Build Handoffs
Device Selection and Execution Target
Part
Custom Platform
Prebuilt Base HW Platform
Advanced Design Management
Concurrent and Iterative Development
Migrating Between Devices
Upgrading Tools
AI Engine Partitions and Runtime Control and Reload
Developing Vitis Kernels
Introduction to Kernels in Vitis
AI Engine Kernel and Graph Development
HLS Kernel Development
HLS Kernel Interface Requirements
Clock and Reset Requirements
Data Driven Kernels
RTL Kernel Development
RTL Kernel Interface Requirements
Control Requirements for XRT-Managed Kernels
Interrupt
Creating User-Managed RTL Kernels
Packaging the RTL Code as a Vitis XO
Design Recommendations for RTL Kernels
Memory Performance Optimizations for AXI4 Interface
Quality of Results Considerations
Debug and Verification Considerations
Vitis Subsystem
Preparing a Vitis Subsystem
Linking a VSS Component
Simulation and Verification in Vitis
Vitis Functional Simulation Overview
VFS Objects
VARRAY Supported Data Types
Debugging with VFS
Simulation with the Vitis Subsystem
Creating and Using Vitis Platforms
Fixed Platforms versus Extensible Platforms
Pre-built Base Platforms
Building Custom Platforms
Platform Creation Basics
Platform Components and Architecture
Extensible Hardware Platforms
Flat Hardware Design Platform
DFX Based Hardware Platform
SSI Technology Devices and Hardware Platforms
Platform Support for Segmented Configuration Flow
Adding Hardware Interfaces
NoC Memory Configuration
Enabling Hardware Emulation
Versal Hardware Platform using a CED Design
Generate XSA
Extensible XSA
Fixed XSA
Software Platform
Creating an Embedded Platform (XPFM)
Validating an Embedded Platform
Validating the Hardware Platform
Check Platform Metadata
Use the Platform with Simple Test Case
Design Validation Using XSA instead of XPFM
Building and Running the System
Integrating AIE and PL Components
Linking the System
After Linking
Linking with the Vitis Integrated Flow
Linking with the Vitis Export to Vivado Flow
Linking the VSS Component to the Platform
Enabling Profile and Debug when Linking
Creating Multiple Instances of a Kernel
Mapping Kernel Ports to Memory
Specifying Streaming Connections
Specifying SLR Region for SSI Devices
Managing Clock Frequencies
Identifying Platform Clocks
Syncing PL Clocks with the AI Engine
Vitis Export to Vivado Flow Detailed Example
Vitis Export Flow Guidelines and Limitations
Managing Vivado Synthesis, Implementation, and Timing Closure
Working with Vivado in the Vitis Integrated Flow
Using the --vivado and --advanced Options
Associating an ELF File with MicroBlaze Processor
Running Multiple Implementation Strategies for Timing Closure
Using --to_step and Launching Vivado Interactively
Integrating the System
Packaging for Vitis Flow
Packaging for Vitis Export to Vivado Flow
Packaging Segmented Configuration
Packaging for DFX Platforms
Deploying and Running the System
Running an Application on the Board
Handling Files and Images for SD Card
Incremental Design Management
Application Verification Using Vitis Emulation Flow
Using Embedded Platforms
QEMU
Building the System in HW Emulation
Packaging the System in HW Emulation
Running the System on Embedded Processor Platform
AI Engine Throughput Estimates
Simulator Support in Hardware Emulation
Using the Simulator Waveform Viewer
Waveform View and Live Waveform Viewer
Generating and Opening the Waveform Reports
Interpreting Data in the Waveform Views
Interpreting TLM Waveform Data for Third-Party Simulators
AXI Transactions Display in XSIM Waveform
Generating Test Vectors for Vitis HLS during Hardware Emulation
Profile and Debug in Hardware Emulation
Using I/O Traffic Generators
Adding Traffic Generators to Your Design
Using Traffic Generators for AI Engine Designs
Using Traffic Generators in AI Engine Graphs
AXI4-Stream I/O Model for Streaming Traffic
Writing Python Traffic Generators
Python API for AI Engine Graphs
Python API for PL Kernels
General Purpose Python API
Writing Traffic Generators in C++
General Purpose C++ API
External RTL Traffic Generators using SV/Verilog
External RTL Traffic Generator and Emulation Process
External RTL Traffic Generator and AI Engine Simulation
Instantiating AI Engine Wrapper in the Test Bench
Generating sim_ipc_axis IP for Vivado Project
Running the RTL Traffic Generator with AI Engine Simulation
Running Traffic Generators in Python/C++
Speed and Accuracy of Hardware Emulation
Profiling and Tracing the Application
Profiling the Application
Enabling Profiling in Your Application
Custom Profiling of the Host Application
Profiling of C++ Code
Profiling of C Code
Enabling NoC-DDRMC Profiling
AI Engine Profiling
Enabling AI Engine Profiling
AI Engine Simulation-Based Profiling
Hardware Emulation and Hardware Run Profiling
HLS Synthesis Report
Generating and Opening the HLS Report
Interpreting the HLS Report
Guidance
Opening the Guidance Report
Interpreting Guidance Data
Tracing The Application
Enabling Trace in Your Application
Continuous Trace Capture
Enabling AI Engine Status Generation
Enabling Trace in AI Engine Based Simulation
AI Engine Event Trace in Hardware
Debugging System Projects
Hardware Profile and Debug Methodology
Stage 1: Design Execution and System Metrics
Stage 2: System Profiling
Stage 3: PL Kernel Analysis
Debugging During Hardware Execution
Checking the FPGA Board for Hardware Debug Support
Enabling Kernels for Debugging with Chipscope
Adding Debug IP to RTL Kernels
Enabling ILA Triggers for Hardware Debug
Pausing the Host Application Using GDB
Debugging with ChipScope
Running XVC and HW Servers
Automated Setup for Hardware Debug
Manual Setup for Hardware Debug
Debugging Designs Using Vivado Hardware Manager
Utilities for Hardware Debugging
Using the Linux dmesg Utility
Using the xrt-smi Utility
Stage 4: AI Engine Event Trace and Analysis
Stage 5: Host Application Debug
Techniques for Debugging Application Hangs
AXI Firewall Trips
Kernel Hangs Due to AXI Violations
Host Application Hangs When Accessing Memory
Typical Errors Leading to Application Hangs
Defensive Programming
Hardware Debug for Embedded Processors
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

Back to home page