This topic introduces key concepts for understanding and using Vitis tools for embedded system design. The tools support a variety of development flows using either scripted execution or interactive design entry through the Vitis IDE. All of the development flows aim for the same outcome, but the designer's skill level and project requirements can influence the preference for a specific flow type. The design steps are described in the following table.
| Step | Comment |
|---|---|
| Select device | Declared as part or board |
| Setup basic hardware infrastructure | Referred to as the hardware platform created with AMD Vivado™ . A valid hardware platform consists of Vivado IP integrator components such as the CIPS, NoC, and at least one clock with associated reset. Optionally, the AI Engine, NoC DDRMC, AXI SmartConnect and AXI Interrupt controller can be added, in addition to clock domains, resets, and custom RTL IP. Within the block design, there will be PFM attributes on cells and ports that define potential attachment points for kernel control, accessing DDR and other memories, streaming input/output, clocks, resets, and interrupts. This initial design is exported to Vitis as an extensible hardware platform. |
| Add processing elements | Referred to as Vitis components, which includes PL Kernels and AI Engine
graphs. Note: These components
are developed and verified independently before being added.
Component development is not in scope of this
document.
|
| Implement Hardware | In Vitis terminology, this is the process of compiling and linking the hardware system. The Vitis implementation step leverages Vivado for PL synthesis and place and route. |
| Add Software Applications | Control and/or processing applications running on processors like APU, RPU, and MicroBlaze. |
| Package Software and Hardware | The process of combining loadable object and executable applications to a binary deliverable like SD Card, QSPI Flash, etc. |
| Deploy and Run on target | This step involves loading a binary deliverable and running on hardware or in hardware emulation. The Vitis implementation step leverages Vivado for PL synthesis and place and route. |
The following figure demonstrates a conceptual flow for designing and integrating an embedded system with AMD tools.
Figure 1.
Vitis Conceptual Design
Flow
Vitis tools support different design flows as described in Vitis Flows and Build Environment. The tools and techniques for creating and integrating these different components are the focus of the following sections.
Terminology for Embedded System Design
The following introduces some of the tools and terms you will encounter in this document.
- Vitis core development kit
- Provides a framework for designing, building, and debugging heterogeneous applications using standard programming languages for both software and hardware components.
- Vivado Design Suite
- An RTL language design, synthesis, and implementation tool that enables hardware designers to create and export hardware designs (.xsa).
- Hardware Design File (.xsa)
- Is a hardware container exported from the Vivado Design Suite for multiple uses, including in a fixed or extensible platform.
- Fixed Platform (.xpfm)
- Includes a completed hardware design (.xsa) and supporting software files defining the operating system, libraries, and boot files. In this context, "fixed" simply means that the hardware design is complete.
- Extensible Platform (.xpfm)
- The target platform of the Vitis heterogeneous system design flow. In this context, the "extensible" design can be further customized by adding programmable content such as PL kernels and AI Engine graph applications to the platform to build the embedded system. Extensible Platform can also be used to develop software like the fixed platform.
- PL kernel (
.xo) - A hardware function that can be added to the PL region of an extensible platform to define custom hardware. PL kernels can be defined using C++ code in Vitis HLS, or using RTL code and the IP packager feature of the Vivado Design Suite.
- Vitis HLS
- A high-level synthesis tool that translates C/C++ functions into RTL for implementation in the programmable logic (PL) region of a device. Vitis HLS generates a compiled object (.xo) file that can be imported into the Vitis environment.
- Vitis Compiler
- The
v++command used to compile PL kernels (.xo) from C++ code, and to link multiple PL kernels with hardware platforms and AI Engine graph applications to build the device binary. - PS Application
- A user-defined software application to be run on an Arm processor in an AMD MPSoC or adaptive SoC device, that can control and interact with PL kernels and AI Engine graph.
- Xilinx Runtime library (XRT)
- Provides an API and drivers to let your software application control, transfer data to, and read the status of the PL kernels and AI Engine graph application in the hardware design.
- AI Engine kernel and graph applications
- Compiled by the Vitis
aiecompilerand linked into the embedded system withv++. Kernels are functions that run on Versal AI Engines and form the fundamental building blocks of a data flow graph application. The AI Engine graph application is an adaptive dataflow graph with deterministic behavior. -
aiecompiler/aiesimulator - Vitis tools for the compilation and simulation of AI Engine graph applications.
- Vitis Subsystem (VSS)
- A platform-independent, reusable design component that targets a specific part and combines AI Engine and/or programmable logic (PL) kernels, or other VSSs. It is compiled and linked with v++ into a .vss library component.
- Vitis Functional Simulation (VFS)
- Toolset for functional simulation and verification of AI Engine graphs and HLS PL kernels using MATLAB or Python environment.
- Device Binary (.xclbin) file
- Contains the programmable device image (PDI) for Versal adaptive SoC or the bitstream for
Zynq MPSoC, and metadata needed to
control the hardware design. Metadata-only
.xclbinfiles can be used for runtime control of a loaded PDI image.