The Vitis Integrated Flow prioritizes ease of use and automation for rapid prototyping and deployment. The flow uses a prebuilt Vivado base platform design, or you can reuse a custom Vivado platform. Vitis handles the linking process and automates synthesis and implementation through a temporary Vivado project, which minimizes user interaction. The following figure shows a simplified overview of the flow.
This flow starts when you select a device part or board. For AMD development boards, AMD provides ready-to-use base platforms, which eliminates the need to create a platform manually. To include domain definitions, memory reservations, and device-tree customization, the flow injects a boot artifacts container into the Vivado extensible design. This container enables a data-driven approach for declaring processor domains and applying use-case-specific memory reservations and device settings to both the hardware and software projects. The container also includes boot-bin files extracted from the OS build, so the Vitis packager can generate the boot PDI and device-tree overlays for flat designs and hardware emulation. For Segmented Configuration designs, the boot PDI comes directly from the OS, while the Vitis packager generates the PL and AIE binaries and their corresponding overlays. For the steps to create a custom platform, see Building Custom Platforms.
Next, Vitis applications extend the hardware design with a modular, heterogeneous subsystem composed of PL kernels and AIE graphs, and provide an environment for software application development, verification, and debug. Developing Vitis Kernels describes how to design and compile the subsystem, and Integrating AIE and PL Components describes how to connect it to the hardware design. In addition, host application development requires the dependencies described in Software Platform.
wic tools
instead.Finally, you deploy and run the system on the hardware or in the hardware/software simulator called the Vitis hardware emulator. For more information, see Deploying and Running the System.
Key features of this flow include:
- Rapid prototyping and deployment: prebuilt or custom Vivado base platform designs accelerate development.
- Automated linking: Vitis handles synthesis and implementation, which minimizes user interaction.
- Modular heterogeneous subsystems: extend the hardware design with PL kernels and AIE graphs.
- Integrated software development environment: develop, verify, and debug software applications.
- Deliverable package creation: combine hardware binaries and software executables for easy deployment.
While the Vitis Integrated Flow fully
supports AMD
Versal and MPSoC embedded software flows, the Xilinx Runtime (XRT) offers complementary Linux
userspace APIs for controlling Vitis components
packaged into xclbin binaries. XRT eliminates the
need for custom kernel drivers or device trees for the Vitis content and provides a compact, readable host application
coding style.
For more fine-grained control over synthesis and implementation in Vivado, see the Vitis Export to Vivado Flow.