Versal Hardware Platform using a CED Design - 2025.2 English - UG1701

The Configurable Example Design (CED) serves as a valuable resource for creating a flat extensible hardware designs in Vivado. This design acts as a reference for demonstrating the configuration of processing system IPs and the connections between them.

The CED offers a practical example for understanding the intricacies of IP configurations and their interconnectedness. It allows you to follow along with the settings of complex processing system IPs. You can gain insights on how the settings should be configured and connected within a flat hardware design.

1. 1. Click File > Project > Open Example, or click Open Example Project from the Quick Start screen.
      
      
   2. Click Next on the Create an Example Project screen.
   3. Select Versal Extensible Embedded Platform in the Select Project Templates window.
      
      
   4. Input the project name and project location. Keep Create project sub-directory checked. Click Next.
   5. Select the target evaluation board in the Default AMD board window. In this example design, select Versal VCK190 Evaluation Platform. Click Next.
      
      
   6. In the Select Design Preset section, set the following design options:

      Clocks

      You can enable clocks, update the output frequency and define default clock in this view. Clock clk_out1is set to 625 MHz by default. For AI Engine -based designs, it is recommended to set the clock to 625 MHz. This enables addition of the MBUFGCE clock buffer in the clock wizard to generate 625 MHz, 312.5 MHz, 156.25 MHz and 78.125 MHz. In this example, clk_out2 and clk_out3 are enabled with Output Frequency 100 MHz and 200 MHz respectively.

      Design type

      If the BDC (Block Design Container) option is left unselected a flat design is generated. If you select the BDC option, a BDC based design is generated which is explained in the next section.

      Configure Interrupt Settings

      Choose interrupts as per the design requirement. The example design supports following:

      • 15 and 32 interrupts, which uses single interrupt controller only.
      • 63 interrupts, which uses two interrupt controller in cascade.

      AI Engine Block

      This block is selected by default.
      
      

   7. Click Next.
   8. Review the project summary and click Finish.
      
      
   9. Observe the following sections in the generated design in the IP integrator:

      AI Engine IP Block

      The AIE IP block is instantiated in the design, which is connected to CIPS through cips_noc. A configuration port used by CIPS using the cips_noc IP to configure the AI Engine IP.

      Memory Section

      Two types of DDR memory controllers are instantiated in the design: DDR4 and LPDDR4 through noc_ddr4 and noc_lpddr4 NoC IPs respectively. These memory controllers are connected to the CIPS IP through cips_noc. You can adjust the memory controller configuration through the noc_ddr4 and noc_lpddr4 settings. In this example, the default NoC settings are used.

      Clock Section

      Three clocks have been generated using the clock wizard.

      Interrupt Section

      Review the section and confirm the settings.

Review Platform Setup

The steps below review the hardware design and confirm that all the appropriate platform properties and tags have been set.

1. AXI port settings:
   • In noc_ddr4 IP, ports S00_AXI to S13_AXI are enabled and SPTAG value is set to DDR.
   • In icn_ctrl IP, portsM01_AXI to M15_AXI are enabled and set to M_AXI_GP. The SP Tag should be left empty. These ports are the AXI master interfaces used to control PL kernels.
     
     
2. In the Clock tab, clk_out1_o1, clk_out1_o2, clk_out1_o3, clk_out1_o4, clk_out2, clk_out3 from clk_wizard_0 are enabled with id {0,3,4,5,1,2}, and frequency {625 MHz, 312.5 MHz, 156.25 MHz, 78.125 MHz, 100 MHz, 200 MHz}. clk_out1_o2 is the default clock. The v++ linker uses this clock to connect the kernel if there are no clocks specified in the link configuration. The Proc Sys Reset property should be set to the synchronous reset signal associated with each clock. The clock status fixed_non_ref indicates that v++ linker cannot use these clocks as a reference to generate a requested clock during the linking phase, it can be used only to connect to IPs. The clock status fixed indicates that v++ linker can use these clocks as a reference clock as well as to connect IPs as defined in system.cfg. Refer Managing Clock Frequencies for more details.
   
   
3. Interrupt settings:
   • In the Interrupt tab, confirm that ports In0 to In31 are enabled.
     
     
4. Simulation model:
   • Select the CIPS instance and verify that the ALLOWED_SIM_MODELS in the Properties tab, in the Block Properties window is tlm, and rtl, and the SELECTED_SIM_MODEL is tlm. It is mandatory to select the same simulation model for NoC and AI Engine.