Validating the Hardware Platform - 2025.2 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)

Document ID
UG1701
Release Date
2025-11-20
Version
2025.2 English

The hardware platform design you created in a Vitis platform is static after the platform creation process is complete.

Vitis does modify parameters based on certain IPs (for example, SmartConnect, NoCs) by adding additional master/slave interfaces. In some situations, PS/CIPS interfaces can also be modified and AMD Versal™ adaptive SoC and AI Engine IP is instantiated in the platform.

The following table shows the workflows to validate the hardware platform design on your board.

Table 1. Platform Workflows
Workflow Development Validation
Basic board bring-up Processor basic parameter setup. Standalone Hello world and Memory Test application run properly.
Advanced hardware setup Enable advanced I/O in Processing System (such as USB, Ethernet, Flash, PCIe® , or RC).

Add I/O related IP in PL (such as MIPI, EMAC, or HDMI_TX).

Add non-Vitis IP (such as AXI block RAM Controller, or Video Processing Subsystem (VPSS) IP).

If these IP have standalone drivers, test them.
Software setup Create PetaLinux project based on hardware platform.

Enable kernel drivers.

Configure boot mode.

Configure rootfs.

Linux boots up successfully.

Peripherals work properly in Linux.