The software platform provides the foundation for running applications on AMD-powered Versal and ZynqMP devices. The platform defines the environment for running and controlling kernels, acts as the control mechanism for fixed and extensible platforms, and includes the domain setup and boot components for initializing, resetting, and configuring the hardware platform.
The software platform includes the following key elements:
- System device tree
- Defines the components and configurations of your hardware so that the software can interact with it.
- Board support package (BSP)
- Contains libraries and drivers specific to your platform that provide access to peripherals, memory management, and processor communication.
- Operating system and boot components
- Manage how the software loads and runs on your platform. The Linux option offers extensive features, and the bare-metal and RTOS options provide more focused control and real-time performance.
Operating System and Processor Support
The software platform supports the following operating systems across different processors:
- Bare-metal
- Suited to resource-constrained applications. Runs on the APU, RPU, and PMC processors and provides a basic single-threaded environment.
- Linux
- Designed for multi-user and multitasking environments. Runs on the APU processors and uses open-source drivers for all processing system peripherals.
- RTOS
- Supports applications that require deterministic scheduling and low latency, typically on APU, RPU, and PMC processors.
Bare-Metal
AMD provides a bare-metal software stack included in the AMD Vitis tools package. The stack is a simple, single-threaded environment tailored for resource-constrained hardware, and provides standard input/output and access to essential processor hardware features. It includes board support packages (BSPs) that contain standalone drivers and libraries. You can configure these components to provide the required functionality with minimal overhead and efficient resource use. The stack is designed for the RPU and APU processors that are commonly found in embedded systems. The Vitis Python API replaces the XSCT command-line tool to configure and build the BSPs.
For details, see Bare-Metal Software Stack in the Versal Adaptive SoC System Software Developers Guide (UG1304).
For details about the Vitis Python API CLI tool and the steps to configure and package the bare-metal BSP, see Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400).
The bare-metal drivers are in the following location of the Vitis install:
<Vitis_Installation_Directory>\<version>\Vitis\data\embeddedsw\XilinxProcessorIPLib\driversThe bare-metal libraries are in the following path:
<Vitis_Installation_Directory>\<version>\Vitis\data\embeddedsw\lib\sw_servicesLinux-Based
The Linux-based software platform is supported on the APU processors of both Versal and Zynq UltraScale+ MPSoC devices. You can also generate the software platform components using Yocto/EDF, PetaLinux, or other third-party frameworks. To control AI Engine graphs or PL kernels from a software application running on Linux with the XRT API, you must add or create a domains YAML file and a ZOCL template. The Vitis packager uses these files to configure and enable the XRT drivers in the software platform.
This platform consists of:
- Root file system (RFS)
- Includes the essential binaries, libraries, and configurations for a functional Linux file system.
- Kernel image
- The compiled Linux kernel with supported peripheral drivers.
- Sysroot
- Lets you cross-compile the host application and provides the libraries required to compile applications for the target system.
For more details, see AMD EDF and PetaLinux Tools Documentation: Reference Guide (UG1144).
All prebuilt AMD platforms include a software platform. By default, the platforms have a Linux domain with the Xilinx Runtime (XRT) enabled, so that applications can run on the platform. Because the device tree is unique to each platform and customer use case, the platform configuration is provided as a machine YAML description, and the user preferences are provided as a domain YAML description. This approach enables hardware customization while sharing a common software platform. You can download common software platform images from the Embedded Platforms download page.
The source files for embedded platforms are available on GitHub at AMD Yocto HW Platforms. For legacy PetaLinux, see Vitis Embedded Platform Source. You can use these files as a reference for your custom software platform development.
RTOS
The FreeRTOS BSP provides a lightweight, multi-threaded environment tailored for embedded systems. It offers basic functions such as standard input and output, and access to processor hardware features. The BSP and its associated libraries are highly configurable so that you can achieve the required functions with minimal resource overhead.
The FreeRTOS software stack closely resembles the bare-metal stack, but adds the FreeRTOS library to enable real-time multitasking. You can integrate AMD device drivers from the standalone libraries with FreeRTOS, provided that only a single thread requires access to the device.
For more details about the FreeRTOS software stack, see FreeRTOS Software Stack in the Versal Adaptive SoC System Software Developers Guide (UG1304).
Boot Components
The software platform components are compiled as binaries and are packaged with the hardware platform into device images. The AMD boot image format (BIF) file stitches binary files together to generate device boot images. Bootgen defines the properties, attributes, and parameters used to create boot images for an AMD device.
The following is an example of a BIF file that targets a Zynq UltraScale+ MPSoC device:
the_MCS_image:
{
[bootloader, destination_cpu=a53-0] <plnx-proj-root>/images/linux/zynqmp_fsbl.elf
[pmufw_image] <plnx-proj-root>/images/linux/pmufw.elf
[destination_device=pl] <plnx-proj-root>/project-spec/hw-description/project_1.bit
[destination_cpu=a53-0, exception_level=el-3, trustzone] <plnx-proj-root>/images/linux/bl31.elf
[destination_cpu=a53-0, load=0x00100000] <plnx-proj-root>/images/linux/system.dtb
[destination_cpu=a53-0, exception_level=el-2] <plnx-proj-root>/images/linux/u-boot.elf
}The following is an example of a BIF file that targets a Versal device:
the_ROM_image:
{
{ type=bootimage, file=<system_project_path>/system.pdi }
}
image
{
name=aie_image, id=0x1c000000
{ type=cdo
/* The following commented lines show the CDOs used to create a merged CDO 'aie.cdo.merged.bin'. For debugging,
uncomment these CDOs and comment the line that adds 'aie.cdo.merged.bin'. */
/*
file = <aie_project_path>/package/libadf/sw/aie.cdo.reset.bin
file = <aie_project_path>/package/libadf/sw/aie.cdo.clock.gating.bin
file = <aie_project_path>/package/libadf/sw/aie.cdo.error.handling.bin
file = <aie_project_path>/package/libadf/sw/aie.cdo.elfs.bin
file = <aie_project_path>/package/libadf/sw/aie.cdo.init.bin
*/
<aie_project_path>/package.hw/aie.merged.cdo.bin
}
}
image
{
name=default_subsys, id=0x1c000000
{ load=0x1000, file=<project_path>/system.dtb }
{ core=a72-0, exception_level=el-3, trustzone, file=<project_path>/boot/bl31.elf }
{ load=0x8000000, core=a72-0, exception_level=el-2, file=<project_path>/boot/u-boot.elf }
}
For the steps to integrate a hardware platform with the software platform and generate boot images for the board, based on the Vitis flow you use, see Integrating the System.