Simulator Support in Hardware Emulation - 2025.2 English

Enabling Third-Party Simulators

Third-party simulators are supported in the AMD Vitis™ Hardware Emulation flow. There are specific settings around third-party simulators that need to be provided in the AMD Vitis™ configuration file. The AMD Vitis™ Unified IDE also supports hardware emulation flow using third-party simulators. Third-party simulators such as Questa Advanced Simulator (Mentor Graphics), Xcelium (Cadence), VCS (Synopsys), and Riviera Simulator (Aldec) are supported when executing hardware emulation of your design. For more details, see the Vivado Design Suite User Guide: Logic Simulation (UG900) for third-party simulator setup.

You can enable these simulators by updating the AMD Vitis™ configuration file (config.ini or system.cfg). When the settings are added to the AMD Vitis™ configuration file, build the design using the v++ link and package flow as described in the script launch_hw_emu.sh. This will launch hardware emulation using the third party simulator specified.

The following are the configuration options to enable third-party simulator setup during v++ -link command line flow. To see enabling third party simulators in the AMD Vitis™ Unified IDE, refer to Enabling Third Party Simulators in the Vitis Reference Guide (UG1702).

[advanced]
param=hw_emu.simulator=QUESTA
[vivado]
prop=project.__CURRENT__.simulator.questa_install_dir=<SIMULATOR DIRECTORY>/questa/2025.2/bin
prop=project.__CURRENT__.compxlib.questa_compiled_library_dir=<SIMULATOR LIBRARY DIRECTORY>/questa/2025.2/lin64/lib/
prop=fileset.sim_1.questa.compile.sccom.cores={16}
prop=fileset.sim_1.questa.elaborate.vopt.more_options={-stats=all}
prop=fileset.sim_1.questa.simulate.vsim.more_options={-stats=all}

[advanced]
param=hw_emu.simulator=XCELIUM
[vivado]
prop=project.__CURRENT__.simulator.xcelium_install_dir=<SIMULATOR DIRECTORY>/bin/
prop=project.__CURRENT__.compxlib.xcelium_compiled_library_dir=<SIMULATOR LIBRARY DIRECTORY>/xcelium/25.03.002/lin64/lib/
prop=fileset.sim_1.xcelium.elaborate.xmelab.more_options={-timescale 1ns/1ps -STATUS]

[advanced]
param=hw_emu.simulator=VCS
[vivado]
prop=project.__CURRENT__.simulator.vcs_install_dir=<SIMULATOR DIRECTORY>/vcs/X-2025.06/bin/
prop=project.__CURRENT__.compxlib.vcs_compiled_library_dir=<SIMULATOR LIBRARY DIRECTORY>/vcs/X-2025.06/lin64/lib/
prop=project.__CURRENT__.simulator.vcs_gcc_install_dir=<SIMULATOR DIRECTORY>/synopsys/vg_gnu/X-2025.06/linux64/gcc-9.2.0_64/bin
param=project.alignLibraryPathEnvForVCS=true
prop=fileset.sim_1.vcs.compile.vlogan.more_options={-v2005}

[advanced]
param=hw_emu.simulator=RIVIERA
[vivado]
prop=project.__CURRENT__.simulator.riviera_install_dir=<SIMULATOR DIRECTORY>/riviera/2024.10-lin64/bin/
prop=project.__CURRENT__.compxlib.riviera_compiled_library_dir=<SIMULATOR LIBRARY DIRECTORY>/riviera/2024.10/lin64/lib/
prop=project.__CURRENT__.simulator.riviera_gcc_install_dir=<SIMULATOR DIRECTORY>/riviera/2024.10-lin64/gcc_Linux64/bin/
prop=fileset.sim_1.riviera.simulate.asim.more_options={+access +r}

v++ -link --config system.cfg

You can use the -user-pre-sim-script and -user-post-sim-script options from the launch_emulator.py command to specify Tcl scripts to run before the start of simulation, or after simulation completes. As an example, in these scripts, you can use the $cwd command to get the run directory of the simulator and copy any files needed prior to simulation, or copy any output files generated at the end of simulation.

To enable hardware emulation, you must set up the environment for simulation in the Vivado Design Suite. A key step for setup is pre-compiling the RTL and SystemC models for use with the simulator. To do this, you must run the compile_sim_lib command in the Vivado tool. For more information on pre-compilation of simulation models, refer to the Vivado Design Suite User Guide: Logic Simulation (UG900).

When creating your Versal platform ready for simulation, the Vivado tool generates a simulation wrapper which must be instantiated in your simulation test bench. So, if the top most design module is <top>, then when calling launch_simulation in the Vivado tool, it will generate a <top>_sim_wrapper module, and also generates xlnoc.bd. These files are generated as simulation-only sources and will be overwritten whenever launch_simulation is called in the Vivado tool. Platform developers need to instantiate this module in the test bench and not their own <top> module.