Simulation with the Vitis Subsystem - 2025.2 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)
Document ID
UG1701
Release Date
2025-11-20
Version
2025.2 English

This chapter describes how to get started with simulating PL and AI Engine with VSS. By simulating the AI Engine design together with PL kernels, valuable knowledge of the interaction between the domains can be modeled and visualized.

Attention: Simulating with VSS is an early access feature and can be subject to change.

Simulating the VSS is an independent parallel activity to linking the VSS to an extensible platform allowing for various development strategies. This figure show the context of VSS simulation in the Vitis export to Vivado flow.

Figure 1. VSS Simulation Context Overview

VSS simulation focuses on the simulation and verification work flow for the VSS. VSS simulation shares the steps for creating and compiling the PL kernels and AI Engine graphs, as well as linking the VSS together.

Within the AI Engine work folder, Makefiles corresponding to RTL simulators are generated. Depending on the choice of RTL simulator, one of the Makefiles are compiled to serve as control application during the simulation. This creates a simulation shared object that is attached to the RTL simulator.

The following figure represents the VSS simulation work flow using Vivado simulation project with XSim.

Figure 2. VSS Simulation work flow
  1. Create a Vivado project.
  2. Import VSS using the following code.
    vitis::import_vss <path_to_vss>/<vss_name>.vss
  3. Create a wrapper for the VSS block design.
  4. Add a VSS wrapper and relevant RTL test bench files (for example, RTL test bench, drivers, and monitors) to the project.
  5. Set the simulation top to the test bench.
  6. Setup simulation option.
  7. Launch Vivado simulation.
  8. Optional: open wave configurations and add signal logging.
  9. Run simulation.
  10. Check the results.

Example for setting up a VSS simulation is available on Vitis Tutorials on Github. See https://github.com/Xilinx/Vitis-Tutorials/tree/HEAD/Vitis_System_Design/Feature_Tutorials/02-Vitis_Subsystem_Simulation for details.

To verify incremental changes to the VSS components, the following table illustrates which steps require re-running.

Table 1. Steps Requiring Re-Running
Update type Steps to update and verify Comments
AI Engine graph without PLIO change
  1. Regenerate libadf.a
  2. Recreate VSS
  3. Recompile AI Engine control app
  4. Verify with simulation
  
AI Engine graph with VSS interface change
  1. Regenerate libadf.a
  2. Recreate VSS
  3. Rebuild simulation project
    1. Create new wrapper
    2. Update RTL test bench, drivers, and monitors.
  4. Verify with simulation
 Changes to interfaces require re-running wrapper to expose port updates so it can be connected in test bench.
RTL or HLS Kernel, changes within VSS
  1. Regenerate .xo file
  2. Recreate VSS
  3. Verify with simulation
  
RTL or HLS Kernel, changes VSS interface
  1. Regenerate .xo file
  2. Recreate VSS
  3. Rebuild simulation project
    1. Create new wrapper
    2. Update RTL test bench, drivers, and monitors.
  4. Verify with simulation
 Changes to interfaces require re-running wrapper to expose port updates so it can be connected in test bench.
Test bench updates
  1. Regenerate simulation scripts
  2. Verify with simulation
 Changes to files (RTL test bench, drivers and monitors) are typically detected when running interactively in Vivado.

Comparing AI Engine Graph Control with Simulation

The following table compares AI Engine graph control and graph inputs and outputs with different methods of simulating an AI Engine design.

Table 2. Comparing AI Engine Graph Control with Simulation
Features AIESIM VSS Simulation HW_EMU
Graph control:
graph.init()
graph.run()
graph.wait()
graph.end()
 graph.cpp - C_RTS graph.cpp - C_RTS host.cpp - PS (QEMU)
RTP graph.cpp - C_RTS graph.cpp - C_RTS host.cpp - PS (QEMU)
PLIO File I/O RTL test bench host.cpp - PS (QEMU)
GMIO graph.cpp - C_RTS Not supported host.cpp - PS (QEMU)