This chapter describes various approaches to simulate and verify AMD Vitis™ kernels and subsystems. They are categorized in three levels, Functional, Cycle approximate, and Performance, each serving different purpose in verifying functional and performance of design components prior to integrating them to a larger system. The following table compares the differences and applications of the methods.
| Feature | Applicable to | Verification Type | Comments |
|---|---|---|---|
| Vitis Functional Simulation |
|
Functional | Focuses on functional correctness using x86 simulation and c models for fast simulation in MATLAB or Python environments. Systems are created by instantiating multiple simulation objects and pass data via the simulation test bench. |
| Vitis Model Composer |
|
Functional or Cycle approximate | Vitis Model Composer enable rapid design exploration and can generate images for accelerated verification on hardware. |
| Vitis Subsystem Simulation | VSS component comprising of AI Engine graphs, RTL | Cycle approximate | Uses a RTL test bench to drive and monitor AXI4-Stream traffic to and from a VSS component. Provides a lightweight system simulation to verify cycle approximate PLIO handshaking between PL kernels and AIE graphs. |
| AI Engine testharness | AI Engine graphs | Performance | Uses a pre-built hardware design infrastructure to quickly test AI Engine graphs with PLIO traffic. |
For details, see the corresponding chapters Vitis Functional Simulation Overview, Vitis Model Composer User Guide (UG1483), Simulation with the Vitis Subsystem, and AI Engine Test Harness in the AI Engine Tools and Flows User Guide (UG1076) .