SSI Technology Devices and Hardware Platforms - 2025.2 English - UG1701

Stacked Silicon Interconnect (SSI) technology enhances Versal Adaptive SoCs by allowing the expansion of PL resources with multiple Super Logic Regions (SLR) connected through an interposer layer. Each SLR includes a dedicated PCM (Power Control Module) block that configures its corresponding PL region. The bottom-most SLR is designated as primary, and handles device boot and initialization of other SLRs through their respective PMCs through the NoC. AI Engine capable SSI devices access and program the AI Engine through the PMC in the top SLR. Details on boot flow for SSI devices is available in Versal Devices Using SSI Technology in the Versal Adaptive SoC System Software Developers Guide (UG1304)

Platform Creation with SSI Devices and AI Engine

The physical placement of the AI Engine array above the top SLR necessitates enabling the corresponding NoC connection to AI Engine for configuration and access. Furthermore, it is essential for the HSM0 clock in the top SLR to use the clock frequency equivalent to AIE_REF_CLK_FREQMHZ of the AI Engine IP.

# Example of SLR1 PMC setting for VC2502 device
  set CIPS_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:versal_cips: CIPS_0 ]
  set_property -dict [list \
    CONFIG.PS_PMC_CONFIG { \
      PMC_CIPS_MODE {ADVANCE} \
      PMC_USE_PMC_NOC_AXI0 {1} \
      PMC_USE_PMC_NOC_AXI1 {1} \
      PMC_CRP_HSM0_REF_CTRL_ACT_FREQMHZ {33.333333} \
      PMC_CRP_HSM0_REF_CTRL_DIVISOR0 {36} \
      PMC_CRP_HSM0_REF_CTRL_FREQMHZ {33.333} \
      PMC_CRP_HSM0_REF_CTRL_SRCSEL {PPLL} \
      PMC_HSM0_CLK_ENABLE {0} \
      PMC_HSM0_CLK_OUT_ENABLE {0} \
      SLR1_PMC_CRP_HSM0_REF_CTRL_ACT_FREQMHZ {33.333333} \
      SLR1_PMC_CRP_HSM0_REF_CTRL_DIVISOR0 {36} \
      SLR1_PMC_CRP_HSM0_REF_CTRL_FREQMHZ {33.333} \
      SLR1_PMC_CRP_HSM0_REF_CTRL_SRCSEL {PPLL} \
      SLR1_PMC_HSM0_CLK_ENABLE {1} \
      SLR1_PMC_HSM0_CLK_OUT_ENABLE {0} \
    } \
    CONFIG.PS_PMC_CONFIG_APPLIED {1} \
  ] $CIPS_0

# Example of SLR3 PMC setting for VC2802 device
  set CIPS_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:versal_cips: CIPS_0 ]
  set_property -dict [list \
    CONFIG.PS_PMC_CONFIG { \
      PMC_CIPS_MODE {ADVANCE} \
      PMC_USE_PMC_NOC_AXI0 {1} \
      PMC_USE_PMC_NOC_AXI1 {1} \
      PMC_USE_PMC_NOC_AXI2 {1} \
      PMC_USE_PMC_NOC_AXI3 {1} \
      PMC_CRP_HSM0_REF_CTRL_ACT_FREQMHZ {33.333333} \
      PMC_CRP_HSM0_REF_CTRL_DIVISOR0 {36} \
      PMC_CRP_HSM0_REF_CTRL_FREQMHZ {33.333} \
      PMC_CRP_HSM0_REF_CTRL_SRCSEL {PPLL} \
      PMC_HSM0_CLK_ENABLE {0} \
      PMC_HSM0_CLK_OUT_ENABLE {0} \
      SLR3_PMC_CRP_HSM0_REF_CTRL_ACT_FREQMHZ {33.333333} \
      SLR3_PMC_CRP_HSM0_REF_CTRL_DIVISOR0 {36} \
      SLR3_PMC_CRP_HSM0_REF_CTRL_FREQMHZ {33.333} \
      SLR3_PMC_CRP_HSM0_REF_CTRL_SRCSEL {PPLL} \
      SLR3_PMC_HSM0_CLK_ENABLE {1} \
      SLR3_PMC_HSM0_CLK_OUT_ENABLE {0} \
    } \
    CONFIG.PS_PMC_CONFIG_APPLIED {1} \
  ] $CIPS_0

For details on CIPS and PMC Power Domain Clocks, see PMC Power Domain Clock in the Control, Interface and Processing System LogiCORE IP Product Guide (PG352) .

Associating the Platform with Vitis Kernels

A new PFM attribute that can be applied to BD cells in IP integrator during platform creation. This attribute, named PFM.REGION functions as a string identifier that associates different BD components intended for joint usage.

set_property PFM.REGION {"MY_SLR_TAG"} [get_bd_cells /my_bd_instance_0]

In Vivado sources, the platform design can include a PBLOCK constraint to impose physical constraint on cells. One intended use case of the REGION attribute is to label a control NoC or other IP instance to reside in a specific SLR (PBLOCK), so that a v++ user can specify linker affinity to the instance. Connections from PL kernels to constrained cells provide impetus to the Vivado placer to place kernels in the same PBLOCK. To add Vitis linking specifications to resources, see Specifying SLR Region for SSI Devices.