The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 07/31/2026 Version 2026.1 Respin | |
| Vitis Functional Simulation | The VFS overview, comparison-of-verification-methods table, supported versions/setup, VFS Objects, VARRAY, and Debugging with VFS were pulled from this guide and redirected to the new UG1864 Vitis Functional Simulation User Guide. |
| Mapping Kernel Ports to Memory | Reworded --connectivity.sp guidance, fixed the
conectivity.sp typo, and added Figure 29 (Global Memory Two
Banks) and Figure 30 (Device Hardware Transaction View). |
| Setting Up the Vitis Environment | Reworked install/setup prose (Vivado + Vitis + XRT;
.csh setup scripts). |
| Running an Application on the Board | Running an Application on the Board: Removed the xrt-smi -examine readiness instruction from the boot-flow paragraph to keep the topic focused on embedded bring-up steps. |
| Stage 1: Design Execution and System Metrics | Removed the Linux XRT xrt-smi design-stall paragraph from “Analyzing Design Stalls in Hardware” while preserving the original figure and image keyref content unchanged. |
| Hardware Emulation and Hardware Run Profiling | Standardized AI Engine memory metric naming by replacing write_throughputs/read_throughput with write_bandwidths/read_bandwidths and updated the XSDB example metric key plus related description text to match bandwidth terminology. |
| Stage 2: System Profiling | Corrected an internal naming inconsistency by changing read_bandwidth to read_bandwidths in the AI Engine Metrics table to align with the topic's existing bandwidth metric names. |
| 06/23/2026 Version 2026.1 | |
| Packaging with Vitis and EDF | Combined original topics "Packaging for Vitis Flow"
and "Packaging Segmented Config" into this topic. This topic now documents EDF
multi-stage (Segmented Configuration) and single-stage boot packaging, the XSA
zip-container hand-off, and the new package.apuLinuxEdfMetadata and
package.userDtsPath advanced parameters. |
| Integrating the System | Added a zocl.dtsi row to the System Integration
Packaging Process Files table. Documented the new EDF-based data-driven approach
that regenerates system device tree drivers for the fixed XSA. Listed the SDTgen,
Lopper, and Bootgen invocations the Vitis packager performs from the
container. Added a link to the Vitis Tutorials System Design
tutorials. |
| Prebuilt Base Platforms | Introduced the new <Board>_<Feature> naming convention for 2026.1 prebuilt Vitis embedded platforms aligned with the GitHub source repository. Added a link to AMD Yocto HW Platforms. Noted that kv260_base still requires PetaLinux. Listed the three boards (vck190_base, vck190_base_dfx, vek280_base) that still use the legacy Xilinx naming convention and PetaLinux. |
| Extensible XSA | Added a section describing how to add domain and custom overlays
when using a prebuilt embedded OS. Documented the rirequed
zocl.dtsi zip container layout and the import_files command. Explained
how boot artifacts flow to the Vitis packager through the XSA for
flat designs and hardware emulation. |
| Software Platform | Replaced XSCT with the Vitis Python API for bare-metal BSP configuration. Added Yocto/EDF as a supported Linux generation flow. Documented the domains YAML and ZOCL template required for XRT control. Added an attention note that AMD EDF replaces PetaLinux in the 2026.1 release. Added links to AMD Yocto HW Platforms and AMD EDF. |
| Workflow | Added an introduction to the AMD Embedded Development Framework for transitioning between Linux OS, RTOS, and bare-metal stacks, and added a tip listing best practices for evaluating Vitis kernel portability with the part option, reusing kernels across extensible platforms, and using multistage boot with Segmented Configuration to minimize OS rebuilds. |
| Vitis Key Concepts | Added a new glossary entry for the AMD Embedded Development Framework (EDF) under Terminology for Embedded System Design. |
| Vitis Integrated Flow | Updated Vitis Integrated Flow to describe the boot artifacts container that conveys domain, memory, and device-tree data to the Vivado extensible design and the Vitis packager (including Segmented Configuration handling), and added notes recommending the platform-and-prebuilt-design strategy for custom boards and clarifying that with AMD EDF the Vitis package step no longer creates the SD card or flash image (use the wic tools instead). |
| Vitis Export to Vivado Flow | Expanded the Vitis Export to Vivado Flow topic to describe the post-implementation embedded software flow, including building a custom machine configuration from the extracted system device tree, preparing the OS, boot artifacts, and SDK, and packaging PL and AI Engine binaries with their overlays. |
| Adding Hardware Interfaces | Updated Adding Hardware Interfaces to specify that a platform requires at least one AXI port and one clock to pass platform DRC, and corrected the SmartConnect-to-M_AXI_GP master port maximum to 16. |
| Linking a VSS Component | Updated to reflect that VSS Simulation is now a production feature. |
| Linking with the Vitis Export to Vivado Flow and Extensible XSA | Clarified BD wrapper creation: Verilog is the default language, and a missing aieprj file forces the tool to infer one, which can cause synthesis issues. |