The Vitis subsystem (VSS) enables a bottom-up methodology by providing one or more intermediate integration stages for combining AI Engine graphs, programmable logic (PL) kernels, or another VSS into a subsystem.
You create PL kernels using either HLS or RTL and include them in a Vitis subsystem as packaged kernels (Vitis
.xo). For a description of how to prepare PL
kernels, see HLS Kernel Development and RTL Kernel Development.
To prepare AI Engine graphs, follow the links in AI Engine Kernel and Graph Development. A VSS supports AI Engine partitions, subject to the following conditions:
- Each partition compiles into a
libadf.aarchive that is included when you construct a VSS component. - Partitions must not overlap in column assignment.
- Only one AI Engine instance is allowed, which is reflected in the VSS linker connectivity.
- Simulating a VSS with AI Engine is supported only with a single partition. To simulate a multiple-partition design, you must merge the partitions into a temporary single-partition AI Engine graph.
You can include a VSS within another VSS, where leaf .xo
kernels and libadf.a archives are flattened as siblings in the parent.
You then link the VSS into an extensible platform along with additional Vitis kernels and libadf.a archives as needed.