The Vitis subsystem enables a bottoms-up methodology by providing one or several intermediate integration stages for combining AI Engine graphs, programmable logic kernels, and/or another VSS into a subsystem.
The PL kernels is created using either HLS or RTL, but delivered to Vitis subsystem as packaged kernels (Vitis XO). For a description how to prepare PL kernels, see HLS Kernel Development and RTL Kernel Development
For preparing AI Enginegraphs, follow the links presented in AI Engine Kernel and Graph Development. VSS support AI Enginepartitions, but require special conditions according to the following list.
- Each partition compiles into a
libadf, which need inclusion when linking a VSS component. - Partitions do not overlap in column assignment.
- There is only one AI Engineinstance which is reflected in the VSS linker connectivity.
- Simulating a VSS with AI Engine is only allowed with a single partition. A multiple partition design need to be merged into a temporary single partition AI Engine graph to use with the simulation.
You can create hierarchies by linking a VSS into another VSS. The VSS additively links to a extensible platform. You can combine VSS with additional Vitis kernels when linking the design to a platform.