Managing Vivado Synthesis, Implementation, and Timing Closure - 2024.2 English

Managing Vivado Synthesis, Implementation, and Timing Closure - 2024.2 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)

Document ID

UG1701

Release Date

2025-01-24

Version

2024.2 English

Tip: This topic requires an understanding of the Vivado Design Suite tools and design methodology as described in UltraFast Design Methodology Guide for FPGAs and SoCs (UG949), or the Versal Adaptive SoC Design Guide (UG1273).

All the flows introduced in Vitis Flows and Build Environment use the Vivado Design Suite for synthesis and implementation of the linked system design. The difference is how the user interacts with Vivado tools. In the Vitis Integrated Flow, this is controlled by command line or configuration file argument sections applying strategies and settings, while the Vitis Export to Vivado Flow uses traditional Vivado methods. This document covers how this is managed for the Vitis Integrated Flow.