Managing Clock Frequencies - 2025.2 English - UG1701

For streaming access, the bit-width of the data and clock frequency determines the throughput. The HLS, RTL or AI Engine kernels processing the data need to sustain the throughput to avoid loss of data. The throughput used here is defined as:

For AI Engine, the interface clock frequency is specified on PLIO to determine the DMA scheduling or stream access rate, but the kernel itself always run at AIE Clock. For details see the topic AI Engine-to-PL Rate Matching in the AI Engine Kernel and Graph Programming Guide (UG1079).

Table 1. Clocking Examples for Kernels with Stream Access

Data access type	Design impact for Vitis	Comments
Synchronous single-rate	Connect to platform clocks and data paths	Kernel clocks match the source and destination in the platform.
Synchronous multi-rate	Connect to platform clocks and data paths Optional: Add new clocks Optional: Add DWC Optional: Add FIFO	To reduce the clock rate while maintaining throughput requirements, the bit-width can be increased. Vitis will add a Data Width Converter (DWC) block to manage the relationship between the bit-width and clocks whose frequency is in a powers of 2 relation. If necessary, Vitis will also infer missing clocks. For non powers of 2 relations, you need advanced clocking and handshaking techniques. Refer to Versal Adaptive SoC Clocking Resources Architecture Manual (AM003) and Clocking Wizard for Versal Adaptive SoC LogiCORE IP Product Guide (PG321). Note: A multi-rate design is synchronous if the clocks have rational relation and a common reference (originates from the same PLL/MMCM). If only one of the multi-rate clocks exist in the platform, Vitis will infer a clock wizard to satisfy this condition.
Time division multiplexing	Connect to platform clocks and data paths Optional: Add new clocks Optional: Add DWC Add FIFO or buffers	The kernel exploits running at higher throughput than incoming data by buffering the incoming data and processing each buffer in sequence. This is closely related to multi-rate signal processing, except that having buffers is mandatory. Note: Vitis can infer DWC and additional clocks to support powers of 2 rate changes. The multiplexing mechanism and buffers need to be designed by the kernel developer.
Packet-switching	Need buffers and logic for handling the control and payload.	Similar to multi-rate, but can require clock rate overhead to manage the control headers. Note: Vitis does not support automatically inferring packet switching. The packet handling mechanism need to be designed by the kernel developer.
Asynchronous	Connect to platform clocks and data paths Optional: Add clocks Add CDC Add FIFO	CDC (Clock domain crossing) logic is required to transfer data across unrelated clock domains. The processing kernel throughput needs to be equal or higher than the input data. FIFO buffers need to be inserted to handle differences in throughput and stall handshaking. Refer to Specifying Streaming Connections for adding FIFO. Note: AI Engine is clocked by a separate PLL. Even if the PLIO has same frequency, the phase relation is unknown so CDC are always inserted by Vitis.

Figure 1. Synchronous Single-Rate with Clock from Platform

Figure 2. Synchronous Multi-rate with Clock from Platform and Inferred DWC

Figure 3. Synchronous Multi-rate with Inferred Clocks and CDC

Figure 4. Asynchronous Single-rate with CDC Related to AI Engine PLIO

Note: The figures above are simplified for illustrative purposes. The data produced and consumed can be the same block or multiple blocks. The HLS and AI Engine can interact with as many other kernels as resource and interface permits.

In Vitis, all memory types are modeled as AXI slave interfaces with metadata, and any clock conversion is handled implicitly through the AXI network connecting kernel AXI master to the memory AXI slave. In cases with HLS kernels converting from memory to stream or stream to memory, or if the memory access has contention from several kernels, the HLS kernel coding could need performance optimizations to meet the required access type. This is also true if the access is to a shared resource. For details on connecting memories, refer to Mapping Kernel Ports to Memory. For details on HLS coding, refer to Memory Mapped Interfaces in the Vitis High-Level Synthesis User Guide (UG1399).