Linking with the Vitis Export to Vivado Flow - Linking with the Vitis Export to Vivado Flow - 2026.1 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)

Document ID
UG1701
Release Date
2026-07-31
Version
2026.1 English

In the Vitis Export to Vivado flow, the linker stops before running RTL synthesis and outputs a project archive (VMA file) for export to the Vivado Design Suite. This flow lets you open the Vitis archive in the Vivado tools for directed synthesis, place and route, and timing closure. The Vitis Export to Vivado flow requires custom Versal platforms designed specifically to support this feature.

An example command follows:

v++ --target hw --platform custom_vck190 --link vadd.xo libadf.a --config ./system.cfg \
--export_archive -o hw-vadd.vma
Important: The --export_archive command does not work with the --target hw_emu (-t) option. The tool returns an error when you use these options together.

This command is similar to the prior command, with the following differences:

--export_archive
Specifies the creation of the .vma file to export to the Vivado Design Suite. This option stops v++ from automatically running Vivado synthesis and place and route, and instead lets you manually launch and direct the implementation and timing closure of the design as described in Vitis Export to Vivado Flow.
--platform custom_vck190
The --export_archive command works only with a custom platform compatible with the Vitis export to Vivado flow.
-o hw-vadd.vma
Specifies the output file name for the .vma file produced by the --export_archive command.

The .vma file is imported into the original extensible platform project in the Vivado Design Suite using the vitis::import_archive Tcl procedure. Development can then continue in the Vivado project, including additional design modifications in the custom platform, and arranging simulation. Before running synthesis and implementation, generate a HDL wrapper for the BD and set it as top.

Note: Synthesizing a BD that includes an AI Engine instance requires a valid aieprj present. If Vivado cannot locate the correct aieprj, Vivado generates one to satisfy this requirement. In this case, the connection information does not match the AI Engine design. Pay attention to log messages during synthesis if aieprj files are missing or disassociated.

After implementation and timing closure, the enhanced write_hw_platform -fixed command encapsulates XRT metadata from the .vma file into the output fixed .xsa. Vivado also supports exporting an XSA for the hardware emulation target, which you can use to run emulation in the Vitis tool.

Important:

If the .vma changes or you use an iterative design flow, run vitis::remove_archive_hierarchy to remove the previously imported VMA before importing the updated VMA.

Vitis Export to Vivado Flow Detailed Example further explains the flow.