The following figure shows two paths through the linking process,
starting with the v++ --link command. The first
path is the Vitis Integrated Flow, where the
v++ command links the elements of the system,
automatically launches the Vivado tools for
implementation of the design, and outputs a .xsa
file. The second path is the Vitis Export to
Vivado flow, where the v++ command links the elements of the system and
outputs a .vma file for you to use in the
Vivado tools for synthesis,
implementation, and timing closure. These two paths are explained below.
At the design level, the v++ link
command operates within a Vitis managed region as a
hierarchy in the extensible hardware platform block design. Based on source input
files, the v++ linker instantiates user-defined PL
kernels, configures platform IP such as AI Engine, NoC, and soft interconnects, adds required design
IP for AXI buses, clock domain crossing, data width conversion, and FIFO buffering,
adds networks for hardware debugging, trace, and clocking, and creates connections
between IP within the Vitis managed region.