In hardware, an AI Engine design can include hundreds of processors and interfaces to the programmable logic (PL) fabric and network-on-chip (NoC). The Vitis linker automatically configures the AI Engine IP core interfaces and connects them to the PL, establishing clock associations and wiring, and automatically performing rate-matching through data width and clock conversion.
The Vitis linker integrates compiled Vitis PL and AIE components and the hardware platform into binary containers. Depending on the choice of design flow, the linker creates either an intermediate binary or final binary container.
The linking process is managed through a Vitis IDE system project or with v++ -link command. To add
and connect Vitis components to the system, specify the
connections through configuration files. These configuration files also specify the
clock domains and additional implementation controls to be used during integration and
implementation. The steps for linking the design is described in Integrating AIE and PL Components.