Hardware Profile and Debug Methodology - 2025.2 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)

Document ID
UG1701
Release Date
2025-11-20
Version
2025.2 English

Designs running on AMD Versal™ AI Engine devices can target the AI Engine, PL, and Arm® host. To ensure a design targeting such multi-domain devices is functionally correct and meets the design performance specification, AMD recommends a five-stage profile and debug methodology in hardware.

The stages are as follows:

  1. Design Execution and System Metrics
  2. System Profiling
  3. PL Kernel Analysis
  4. AI Engine Event Trace and Analysis
  5. Host Application Debug
Figure 1. Five Stages of Profile and Debug Methodology

The goal of each stage along with available tools and techniques are described below.