In the Vitis development flow, PL kernels
as compiled object files (.xo) are the processing elements
executing in the programmable logic region of the AMD device. The Vitis core
development kit supports PL kernels written in C/C++ compiled by the v++ HLS compiler, and RTL IP packaged in the Vivado Design Suite.
This section covers PL kernels in C/C++ by HLS compiler, with details on kernel interfaces, clock and reset requirements and host controlling code. Unless otherwise stated, the interface, clock, reset and host code practices in this section can also apply to RTL Kernels, if RTL kernels matches the specific requirements.
For the v++ command to compile C/C++ code
with HLS compiler, refer to
v++ Mode
HLS in the Vitis
Reference Guide (UG1702).