Device Selection and Execution Target - 2025.2 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)
Document ID
UG1701
Release Date
2025-11-20
Version
2025.2 English

The first step when building the application is to specify a target device and what kind of execution target to use. Device selection and corresponding description is done through the following methods:

Table 1. Device Selection and Execution Target
Device selection method v++ Command line option AMD Vitis™ IDE option
Part --part <part_number> Select the Part dialog when creating new Vitis Component, or change in Vitis Component settings.
Custom Platform --platform <platform_name> Select the Platform dialog when creating a new Vitis Component, or change in Vitis Component settings.
Prebuilt Base HW Platform --platform <platform_name> Select the Platform when creating a new Vitis Component, or change in Vitis Component settings.

The execution target of the Vitis tool defines the nature and contents of the FPGA binary output created during compilation and linking. There are two different build targets: one emulation target used for validation and debugging purposes: hardware emulation, and the default system hardware target used to generate the FPGA binary loaded into the AMD device.

The emulation run is performed in a simulation environment, which offers enhanced debug visibility and does not require physical hardware board to launch design execution.

Selecting execution targets is applicable to compile, link and package commands with v++ using the option --target [hw_emu | hw].

Table 2. Comparison of Emulation Flows with Hardware Execution
Hardware Emulation Hardware Execution
Host application runs with a simulated RTL model of the kernels. SystemC models and external TGs are also supported. Host application runs with actual hardware implementation of the kernels.
Test the host / kernel integration, get performance estimates. Confirm that the system runs correctly and with desired performance.
Best debug capabilities with increased visibility of the kernels. Final FPGA implementation with accurate (actual) performance results.

Details on device selection and execution target options are available in v++ General Options in the Vitis Reference Guide (UG1702).