The AMD Vitis™ unified software platform provides application-level debug features and techniques that allow the Application component, AI Engine component, PL kernels, and the interactions between them to be debugged. However, debugging projects built from the command line is a challenge because the various elements of the system, the compiled AI Engine graph application (libadf.a), the device binary (.xclbin), and the top-level application (host.elf), must be gathered together and presented as a system.
The Vitis unified IDE provides an excellent framework for debugging these heterogeneous systems. There are many advantages to working in the Debug view in the IDE. In fact, you are strongly recommended to debug your command-line driven projects in the IDE. The process for doing this is broken down into two steps:
- Import your command-line project into the IDE as described in Getting Started with Vitis in the Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400) .
- Debug the system in the IDE as described in Debugging the System Project and AI Engine Components in the Vitis Reference Guide (UG1702).
The Vitis tools provide application-level debug features which let the host code, the system project, and the interactions between them be efficiently debugged in the Vitis unified IDE. These features and techniques are split between software debugging and hardware debugging flows. The recommended debugging flow consists of three levels of debugging:
- The AI Engine graph can be simulated and debugged on its own using GDB or the trace and profile tools available within the aiesimulator (see Simulating an AI Engine Graph Application in the AI Engine Tools and Flows User Guide (UG1076)). The input and output of the graph can be managed by external traffic generators using C++, Python or Verilog (see External Traffic Generator in the AI Engine Tools and Flows User Guide (UG1076)). This is a first step where the host application is not debugged, but the graph can be debugged using realistic data flows.
- Debugging in Hardware Emulation in the Data Center Acceleration using Vitis (UG1700) to compile the PL kernels into RTL, confirm the behavior of the generated logic, and evaluate the simulated performance of the hardware.
- Debugging During Hardware Execution to implement the device binary and debug the application running on hardware using Xilinx virtual cable (XVC) running over the PCIe® bus, or debugged using USB-JTAG cables for embedded processor platforms.
This three-tiered approach enables debugging the Application component and System project at different levels of abstraction. Each provides specific insights into the design providing a comprehensive view of the system from software to hardware. All flows are supported through the Vitis unified IDE using basic compile time and runtime setup options.