The hardware design that incorporates Dynamic Function eXchange (DFX) technology consists of a static region and a reconfigurable partition(RP) spanning the AI Engine and PL. The static region contains IPs such as CIPS, NoC and memory, while the reconfigurable partition region is where the dynamic PL logic or the AI Engine and its associated PL logic can be placed. For Versal devices that include the AI Engine, the AI Engine must be located in a reconfigurable partition region. Vitis and XRT only support a single reconfigurable partition and expect AIE, if used, to be part of that reconfigurable partition.
Each Vitis linker run creates a reconfigurable module (RM) that can be loaded at runtime in the context defined by the static region. Refer to Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947) to understand the working of DFX design in more detail.
Settings for DFX-Based Platform in Vivado
- Address Aperture Setting
- To ensure that the CIPS and SmartConnect IP can access
kernels in the dynamic region you need to set the address range for the
dynamic region. This involves explicitly setting apertures to DDR memory
interfaces in the static region block design, so that the kernel's
accessible DDR range can be exported. To lock the bus definition
settings, enter the following command in the Tcl
console:
set_property HDL_ATTRIBUTE.LOCKED TRUE [get_bd_intf_pins /<RP BDC name>/PL_CTRL_S_AXI] set_property HDL_ATTRIBUTE.LOCKED TRUE [get_bd_intf_pins /<RP BDC name>/DDR_0] set_property HDL_ATTRIBUTE.LOCKED TRUE [get_bd_intf_pins /<RP BDC name>/DDR_1] set_property HDL_ATTRIBUTE.LOCKED TRUE [get_bd_intf_pins /<RP BDC name>/DDR_2] set_property HDL_ATTRIBUTE.LOCKED TRUE [get_bd_intf_pins /<RP BDC name>/DDR_3]
- Set up Block Design Container (BDC) for DFX
- In Vivado, the hardware design needs to define a Block Design Container (BDC) for the RP. The BDC establishes the dynamic region or RP. The RP consists of a BDC hierarchy managed by Vitis, and to configure it, you must update its properties, set the container boundaries, use the DFX wizard, and include a configuration.
- Set Up Block Design Container (BDC) for DFX
-
# Specify that this platform supports DFX set_property platform.uses_pr true [current_project] # Specify the dynamic region instance path for hardware run set_property platform.dr_inst_path {design_1_i/<RP BDC name>} [current_project] # Specify the dynamic region instance path for emulation set_property platform.emu.dr_bd_inst_path {design_1_wrapper_sim_wrapper/design_1_wrapper_i/design_1_i/<RP BDC name>} [current_project]
Static region and dynamic regions share the DDR memory. An AXI NoC IP is required in the Vitis Region, in the RP, to export the memory interface. The V++ linker connects the PL kernel memory interfaces to the AXI NoC IP to access memory.
- DFX Decoupler IP
- For security reasons, DFX platforms require the DFX Decoupler IP to control kernel operations during reconfiguration. This IP plays a crucial role in ensuring system stability and preventing unexpected behavior.
- DFX Decoupler IP Functions
-
- Disabling communication channels during reconfiguration to avoid unintended requests from the static region that could lead to invalid AXI interface states or cause random toggles due to partial reconfiguration.
- Preventing unexpected side effects by isolating the static and reconfigurable regions, thereby avoiding potential disruptions in the static region caused by reconfiguration.
- Allowing Xilinx Runtime (XRT) control, which automatically activates and deactivates the DFX Decoupler IP before and after reconfiguration, respectively.
In summary, the DFX Decoupler IP serves as a safety measure during reconfiguration, ensuring security and preventing unwanted interactions between the static and reconfigurable regions of the DFX platform.
Vitis Python API DFX Platform Creation Flow
The process for creating a DFX (Dynamic Function eXchange) platform using the Vitis Python API involves three main steps, assuming the Vitis Python API client object is already initialized.
Vitis Python API Flow for DFX Platform Creation
This flow requires referencing both the static hardware design and the reconfigurable partition (RP) XSA files.
Step 1: Add Reconfigurable Partition (RP) Info Arguments
You must first define the arguments specific to the reconfigurable partitions that will be part of the DFX platform. The number of elements here must correspond exactly to the number of reconfigurable partitions defined in your static XSA.
rp_info_args = client.add_rp_info_args(
rp_xsa_path="rp.xsa"
)Step 2: Create the Platform Component with DFX Support
Next, use the create_platform_component command, passing the
rp_info_args created in the previous step to enable DFX
support.
platform = client.create_platform_component(
name="platform_dfx_static",
hw_design="$COMPONENT_LOCATION/../../../xsa/static.xsa",
os="standalone",
cpu="psv_cortexa72_0",
domain_name="standalone_psv_cortexa72_0",
generate_dtb=True,
rp_info_args=rp_info_args,
hw_boot_bin="BOOT.BIN"
)The arguments required for create_platform_component include the following.
- name
- The desired name for the platform component (for example,
platform_dfx_static).
- hw_design
- The path to the static XSA file, which contains the hardware architecture defining the static region.
- os
- Specifies the operating system (for example,
standalone) and the target processor (e.g.,psv_cortexa72_0) for the platform. - cpu
- Specifies the target processor (for example,
psv_cortexa72_0) for the platform.
- rp_info_args
- The list of reconfigurable partition arguments generated in Step 1.
- hw_boot_bin
- The path to the BOOT.BIN. See Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400) and Bootgen User Guide (UG1283) on how to generate the boot image.
Step 3: Retrieve and Build the Platform Component
Retrieve the newly created platform component object and trigger the build process.
platform = client.get_component(name="platform_dfx_static")
status = platform.build()You must update the paths specified for rp_xsa_path and hw_design to
reflect the actual locations of your XSA files.
This script requires that the client object for the Vitis Python API is initialized prior to execution.
The overall definition of the DFX system involves specifying a fixed or static region and detailing the reconfigurable partition (RP).
The end to end flow to create the DFX based design is detailed in the Vitis tutorial https://github.com/Xilinx/Vitis-Tutorials/tree/master/Vitis_Platform_Creation/Design_Tutorials/04_Edge_VCK190_DFX.
For more details on DFX design, refer to Vivado Design Suite User Guide: Dynamic Function eXchange (UG909).