Clock and Reset Requirements - 2025.2 English

Clock and Reset Requirements - 2025.2 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)

Document ID

UG1701

Release Date

2025-11-20

Version

2025.2 English

The following clock and reset requirements apply to both software controllable and non-software controllable kernels.

Table 1. Requirements
HLS Kernel	RTL Kernel
HLS kernel does not require any input from user on clock ports and reset ports. The HLS tool always generates RTL with clock port `ap_clk` and reset port `ap_rst_n`. HLS kernels can only have one clock and reset.	RTL kernels require at least one clock port, but a kernel can have multiple clocks. The number of clocks that an RTL can have is primarily determined by the number of clocks that the platform supports. Most embedded platforms can have multiple clocks. An active-Low reset port can optionally be associated with a clock through the `ASSOCIATED_RESET` parameter on the clock.