Building and Running the System - Building and Running the System - 2026.1 English - UG1701

Embedded Design Development Using Vitis User Guide (UG1701)
Document ID
UG1701
Release Date
2026-07-31
Version
2026.1 English

The AMD Vitis™ tool simplifies hardware design and integration with a software-like compilation and linking flow that integrates the four domains of the AMD Versal™ device: the AI Engine array, the programmable logic (PL) region, the network-on-chip (NoC), and the processing system (PS). The Vitis linker flow lets you integrate your compiled AI Engine design graphs (libadf.a) with additional kernels implemented in the PL region of the device, including HLS and RTL kernels, and link them for use on a target platform. The Vitis linker provides abstract directives for accessing system memory, CPU control, and streaming I/O, so you can often develop AI Engine graphs and kernels on a standard development platform and quickly retarget the AI Engine code to a custom platform that you develop for your application. You can control AI Engine graphs and PL kernels from code running on an embedded Arm® processor on the Versal device or from an external CPU.

The following figure shows the high-level steps to use the Vitis tools flow to integrate your application. This topic describes the command-line process to run this flow.
Note: You can also use this flow from within the Vitis IDE, as explained in Launching Vitis Unified IDE in the Vitis Reference Guide (UG1702).
Figure 1. Vitis Integrated Flow

Note: Run the application on hardware or in the emulator.
Important: Using Vitis tools and AI Engine tools requires the setup described in Setting Up the Vitis Environment.

You can adapt the following steps to any Vitis project that targets a Versal device.

  1. AMD provides Prebuilt Base Platforms for select devices and recommends that you use the Vitis Integrated Flow. Target the pre-built embedded base platforms that the Vitis installer installs, or target a Custom Platform that you create.
  2. As described in Compiling an AI Engine Graph Application in the AI Engine Tools and Flows User Guide (UG1076), first create and compile the AI Engine graph into a libadf.a file with the AI Engine compiler. Iterate between the AI Engine compiler and the AI Engine simulator to develop the graph until you are ready to proceed.
  3. PL kernel compilation: Compile PL kernels for implementation in the PL region of the target platform with the v++ --mode hls command. See HLS Kernel Development. In addition to Vitis compilation, you can use Vivado to package RTL modules as kernels in the compiled .xo format, as described in Packaging the RTL Code as a Vitis XO. See v++ Mode HLS in the Vitis Reference Guide (UG1702).
  4. Linking the System: Link the compiled AI Engine graph with the HLS and RTL kernels onto a target platform. This process creates an XSA file that encapsulates the implemented hardware system, which lets you create boot and loadable images.
    Note: During linking, the tool performs a NoC design rule check. For more information, see Validate NoC DRCs in the Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387) .
  5. PS application compilation: Optionally, compile a host application to run on the Cortex®-A72 core processor with the GNU Arm cross-compiler to create an ELF file. The host program interacts with the AI Engine kernels and the kernels in the PL region. This step is optional because you can deploy and interact with the AI Engine kernels in several ways; a host program running on the PS is one option.
  6. Packaging with Vitis and EDF: Use the v++ --package process to gather the files needed to configure and boot the system and to load and run the application, including the AI Engine graph and PL kernels. You can also invoke the packager to build the package needed to run emulation and debug or to run your application on hardware.