Working with Vivado in the Vitis Integrated Flow - 2024.2 English - UG1700

The Vitis Integrated Flow automatically launches the Vivado Design Suite to synthesize the linked system design, place and route the elements of the design, resolve timing, and generate the bitstream for the design. In most cases, the Vitis Integrated Flow completely abstract away the underlying process of synthesis and implementation of the hardware design. This removes the application developer from the typical hardware development process and the need to manage constraints such as logic placement and routing delays. The Vitis Integrated Flow automates much of the FPGA implementation process.

While automated, this flow does offer some opportunity for manual intervention. The process is broken down into a series of major steps that can be interrupted to enable customization when necessary. In some cases, you may want to exercise some control over the synthesis and implementation processes deployed by the Vitis linker, especially when large designs are being implemented. The Vitis Integrated Flow offers some control through specific options that can be specified in a v++ configuration file, or from the command line. The following sections describe some of the methods you can use to control the Vivado synthesis and implementation results.

• Using the --vivado options to manage the Vivado tool.
• Using multiple implementation strategies to achieve timing closure on challenging designs.
• Using the -to_step and -from_step options to run the compilation or linking process to a specific step, perform some manual intervention on the design, and resume from that step.
• Interactively editing the Vivado project, and using the results for generating the FPGA binary.