Vitis Software Platform Installation - 2025.2 English - UG1700

Data Center Acceleration Using Vitis User Guide (UG1700)

Document ID: UG1700
Release Date: 2025-11-20
Version: 2025.2 English

Getting Started with Vitis
Navigating Content by Design Process
Vitis Software Platform Installation
Installing the Vitis Software Platform
Installing Xilinx Runtime and Platforms
Setting Up the Vitis Environment
Introduction to Vitis
Introduction to Data Center Acceleration for Software Programmers
Terminology
Working with Alveo Accelerator Cards
A Sample Application
Vitis Application Development Flow
Best Practices for Kernel Development
Best Practices for Host Programming
Next Steps
Introduction to Data Center Acceleration for RTL Designers
Terminology
Vitis Development Flow for RTL Designers
Using Alveo Accelerator Cards
Differences between Vivado and Vitis Development Flows
Creating and Packaging RTL Kernels
Building Kernels and Managing Implementation
Writing Host Applications with XRT API
Next Steps
Introduction to the Vitis Unified IDE
Features
Components and System Projects
System Project Configuration Files
Accelerating Data Center Applications with Vitis Software Platform
Introduction
Acceleration: An Industrial Analogy
Methodology Overview
Recommendations
Methodology for Architecting a Device Accelerated Application
Step 1: Establish a Baseline Application Performance and Establish Goals
Measure Running Time
Measure Throughput
Determine the Maximum Achievable Throughput
Establish Overall Acceleration Goals
Step 2: Identify Functions to Accelerate
Identify Performance Bottlenecks
Identify Acceleration Potential
Step 3: Identify Device Parallelization Needs
Estimate Hardware Throughput without Parallelization
Determine How Much Parallelism is Needed
Determine How Many Samples the Datapath Must Process in Parallel
Determine How Many Kernels To Instantiate in the Device
Step 4: Identify Software Application Parallelization Needs
Minimize CPU Idle Time while the Device Kernels are Running
Keep the Device Kernels Utilized
Optimize Data Transfers to and from the Device
Conceptualize the Desired Application Timeline
Step 5: Refine Architectural Details
Finalize Kernel Boundaries
Decide Kernel Placement and Connectivity
Methodology for Developing C/C++ Kernels
About the High-Level Synthesis Compiler
Verification Considerations
Step 1: Partition the Code into a Load-Compute-Store Pattern
Create a Top-Level Function with the Desired Interface
Code the Load and Store Functions
Match Port Width to Datapath Width
Use Burst Transfers
Minimize the Number of Data Transfers from Global Memory
Code the Compute Functions
Connect the Load, Compute, and Store Functions
Step 2: Partition the Compute Blocks into Smaller Functions
Decompose to Identify Throughput Goals
Aim for Functions with a Single Loop Nest
Connect Compute Functions Using the Dataflow ‘Canonical Form’
Step 3: Identify Loops Requiring Optimization
Step 4: Improve Loop Latencies
Apply Loop Unrolling
Apply Array Partitioning
Step 5: Improve Loop Throughput
Eliminate I/O Contentions
Eliminate Loop-Carried Dependencies
Advanced Techniques
Best Practices for Data Center Acceleration with Vitis
Tutorials and Examples
Developing Vitis Kernels and Applications
Programming Model
Design Topology
PL Kernel Properties
SW-Controllable Kernels
Design Languages
HW Interfaces
Execution Modes
Data Driven Kernels
Kernel Interface Requirements
Clock and Reset Requirements
Writing the Software Application
Specifying the Device ID and Loading the XCLBIN
Setting Up XRT-Managed Kernels and Kernel Arguments
Creating Multiple Compute Units
Transferring Data between Software and PL Kernels
Working with XRT-Managed Kernels
Working with User-Managed Kernels
Summary
Developing PL Kernels using C++
Packaging RTL Kernels
Requirements of an RTL Kernel
Kernel Interface Requirements
Control Requirements for XRT-Managed Kernels
Interrupt
Creating User-Managed RTL Kernels
RTL Kernel Development Flow
Packaging the RTL Code as a Vitis XO
Design Recommendations for RTL Kernels
Memory Performance Optimizations for AXI4 Interface
Quality of Results Considerations
Debug and Verification Considerations
Building and Running the System
Selecting the Build Target
Hardware Emulation Target
Hardware Execution Target
Building the Software Application
Compiling and Linking for x86
Building the Device Binary
Compiling C/C++ PL Kernels
Linking the System
Enabling Profile and Debug when Linking
Creating Multiple Instances of a Kernel
Mapping Kernel Ports to Memory
Additional Memory Mapping Techniques for Alveo Accelerator Cards
Assigning AXI Interfaces to PLRAM
HBM Configuration and Use
Random Access and the RAMA IP
Directly Accessing Host Memory on Alveo Accelerator Cards
Specifying Streaming Connections
Assigning Compute Units to SLRs on Alveo Accelerator Cards
SLR Guidelines for Kernels that Access Multiple Memory Banks
Managing Clock Frequencies
Using --freqhz for Clock Management
Identifying Platform Clocks
Controlling Report Generation
Managing Vivado Synthesis, Implementation, and Timing Closure
Working with Vivado in the Vitis Integrated Flow
Using the --vivado and --advanced Options
Running Multiple Implementation Strategies for Timing Closure
Using --to_step and Launching Vivado Interactively
Running the System on Hardware
Application Verification Using Vitis Emulation Flow
Running Hardware Emulation
Speed and Accuracy of Hardware Emulation
Simulator Support in Hardware Emulation
Using the Simulator Waveform Viewer
AXI Transactions Display in XSIM Waveform
Generating Test Vectors for Vitis HLS during Hardware Emulation
Profiling and Debugging the Application
Profiling the Application
Enabling Profiling in Your Application
Continuous Trace Capture
Custom Profiling of the Host Application
Profiling of C++ Code
Profiling of C Code
Enabling Low Overhead Profiling
Enabling No Overhead Profiling
Guidance
Opening the Guidance Report
Interpreting Guidance Data
System Estimate Report
Opening the System Estimate Report
Interpreting the System Estimate Report
Design and Target Device Summary
Kernel Summary
Timing Information
Latency Information
Area Information
HLS Synthesis Report
Generating and Opening the HLS Report
Interpreting the HLS Report
Profile Summary Report
Generating and Opening the Profile Summary Report
Interpreting the Profile Summary
Timeline Trace
Generating and Opening the Timeline Trace
Interpreting the Timeline Trace
Detailed Kernel Trace
Using Burst Data Transfers
Using Full AXI Data Width
Waveform View and Live Waveform Viewer
Generating and Opening the Waveform Reports
Interpreting Data in the Waveform Views
Interpreting TLM Waveform Data for Third-Party Simulators
Debugging System Projects
Debugging in Hardware Emulation
Enable Waveform Debugging with the Vitis Compiler Command
Running Live Waveform Mode
Debug Techniques for Hardware Emulation
Debugging During Hardware Execution
Enabling Kernels for Debugging with Chipscope
Adding Debug IP to RTL Kernels
Enabling ILA Triggers for Hardware Debug
Adding ILA Triggers Before Starting Kernels
Pausing the Host Application Using GDB
Debugging with ChipScope
Checking the FPGA Board for Hardware Debug Support
Running XVC and HW Servers
Automated Setup for Hardware Debug
Manual Setup for Hardware Debug
Starting Debug Servers on an Amazon F1 Instance
Debugging Designs Using Vivado Hardware Manager
JTAG Fallback for Private Debug Network
JTAG Fallback Steps
Utilities for Hardware Debugging
Using the Linux dmesg Utility
Using the xrt-smi Utility
Techniques for Debugging Application Hangs
AXI Firewall Trips
Kernel Hangs Due to AXI Violations
Host Application Hangs When Accessing Memory
Typical Errors Leading to Application Hangs
Defensive Programming
Additional Information
Migrating from Existing Tools
Terminology Changes
Control File Differences
Migrating Projects from Classic IDE
Migrating to a New Target Platform
Design Migration
Understanding an FPGA Architecture
Understanding Target Platforms
Migrating Releases
Host Code Migration
Release Migration
Modifying Kernel Placement
Implications of a New Hardware Platform
Determining Where to Place the Kernels
Assigning Kernels to SLRs
Address Timing
Custom Constraints
Timing Closure Considerations
OpenCL Programming
OpenCL Host Application
OpenCL Installable Client Driver Loader
Setting Up the OpenCL Environment
Platform
Devices
Sub-Devices
Context
Command Queues
Program
Executing Commands on the FPGA
Setting Up Kernels
Setting Kernel Arguments
Buffer Allocation on the Device
Buffer Creation and Data Transfer
Letting XRT Allocate Buffers
Using Host Pointer Buffers
Allocating Page-Aligned Host Memory
Sub-Buffers
Reading a Specific Portion from the Device Buffer
Device Buffer Shared by Multiple Memory Ports or Multiple Kernels
Optimizing Data Movement
Overlapping Data Transfers with Kernel Computation
Buffer Memory Segmentation
Kernel Execution
Reducing Overhead of Kernel Enqueing
Task Parallelism Using Different Kernels
Spatial Data Parallelism: Increase Number of Compute Units
Temporal Data Parallelism: Host-to-Kernel Dataflow
Enabling Host-to-Kernel Dataflow
Symmetrical and Asymmetrical Compute Units
Kernel Handle and Compute Units
Using Compute Unit Name to Get Handle of All Asymmetrical Compute Units
Compute Unit Scheduling
Multiple In-Order Command Queues
Single Out-of-Order Command Queue
Event Synchronization
Debugging OpenCL Kernels
Assigning DDR Bank in Host Code
Assigning Global Memory for Kernel Code
Creating Multiple AXI Interfaces
Post-Processing and FPGA Cleanup
Compiling and Linking the Host Application
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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