The Vitis
development flow enables development of FPGA-accelerated data center applications. In
this environment, a software application running on an x86 processor uses the Xilinx Runtime (XRT) API to offload compute intensive
tasks to execute a hardware kernel running on the programmable logic (PL) of an AMD data center accelerator card.
The elements of these FPGA-accelerated systems include the following:
- AMD Alveo™ Data Center accelerator cards
- Software applications using XRT running on x86 processors on AMD Adaptive SoC devices, as described in Writing the Software Application
- Programmable logic acceleration functions developed in RTL as described in RTL Kernel Development Flow
- Programmable logic acceleration functions as described in Developing PL Kernels using C++
- The Vitis tools to compile and link the various elements as described in Building and Running the System, or Creating a System Project for Heterogenenous Computing in the Vitis Reference Guide (UG1702)