Programming Model - 2024.2 English

Data Center Acceleration Using Vitis User Guide (UG1700)

Document ID
UG1700
Release Date
2025-01-15
Version
2024.2 English
The Vitis development flow enables development of FPGA-accelerated data center applications. In this environment, a software application running on an x86 processor uses the Xilinx Runtime (XRT) API to offload compute intensive tasks to execute a hardware kernel running on the programmable logic (PL) of an AMD data center acceleration card.

The elements of these FPGA-accelerated systems include the following: