Tip: This topic requires an
understanding of the Vivado Design Suite tools
and design methodology as described in
UltraFast Design Methodology Guide for FPGAs and SoCs
(UG949).
The Vitis linking process use the Vivado Design Suite for synthesis and implementation of the linked system design.
When building a device binary for an AMD data-center acceleration card, the system design is automatically
synthesized and implemented in the Vivado Design Suite during the v++
linking phase.
Figure 1.
Vitis Integrated
Flow
